@@ -690,8 +690,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
- /* some are required yet no dependencies were declared */
- clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
@@ -567,35 +567,70 @@ static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
static int __init mpc512x_psc_fifoc_init(void)
{
struct device_node *np;
+ struct clk *clk;
np = of_find_compatible_node(NULL, NULL,
"fsl,mpc5121-psc-fifo");
if (!np) {
pr_err("%s: Can't find FIFOC node\n", __func__);
- return -ENODEV;
+ goto out_err;
+ }
+
+ clk = of_clk_get_by_name(np, "per");
+ if (IS_ERR(clk)) {
+ pr_err("%s: Can't lookup FIFO clock\n", __func__);
+ goto out_ofnode_put;
+ }
+ if (clk_prepare_enable(clk)) {
+ pr_err("%s: Can't enable FIFO clock\n", __func__);
+ goto out_clk_put;
}
psc_fifoc = of_iomap(np, 0);
if (!psc_fifoc) {
pr_err("%s: Can't map FIFOC\n", __func__);
- of_node_put(np);
- return -ENODEV;
+ goto out_clk_disable;
}
psc_fifoc_irq = irq_of_parse_and_map(np, 0);
- of_node_put(np);
if (psc_fifoc_irq == 0) {
pr_err("%s: Can't get FIFOC irq\n", __func__);
- iounmap(psc_fifoc);
- return -ENODEV;
+ goto out_unmap;
}
+ clk_put(clk);
+ of_node_put(np);
return 0;
+
+out_unmap:
+ iounmap(psc_fifoc);
+out_clk_disable:
+ clk_disable_unprepare(clk);
+out_clk_put:
+ clk_put(clk);
+out_ofnode_put:
+ of_node_put(np);
+out_err:
+ return -ENODEV;
}
static void __exit mpc512x_psc_fifoc_uninit(void)
{
+ struct device_node *np;
+ struct clk *clk;
+
iounmap(psc_fifoc);
+
+ /* disable the clock, errors are not fatal */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-psc-fifo");
+ if (np) {
+ clk = of_clk_get_by_name(np, "per");
+ if (!IS_ERR(clk)) {
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+ }
+ of_node_put(np);
+ }
}
/* 512x specific interrupt handler. The caller holds the port lock */
prepare and enable the FIFO clock upon PSC FIFO initialization, disable and unprepare the FIFO clock upon PSC FIFO uninitialization, remove the pre-enable workaround from the platform's clock driver Signed-off-by: Gerhard Sittig <gsi@denx.de> --- arch/powerpc/platforms/512x/clock-commonclk.c | 2 -- drivers/tty/serial/mpc52xx_uart.c | 47 +++++++++++++++++++++---- 2 files changed, 41 insertions(+), 8 deletions(-)