From patchwork Wed Jul 17 17:10:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soren Brinkmann X-Patchwork-Id: 2828895 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3F14D9F967 for ; Wed, 17 Jul 2013 17:12:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0B1502025A for ; Wed, 17 Jul 2013 17:12:37 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DFAE32031C for ; Wed, 17 Jul 2013 17:12:35 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UzVGN-0005UH-Tq; Wed, 17 Jul 2013 17:11:41 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UzVGB-0002gb-Ib; Wed, 17 Jul 2013 17:11:27 +0000 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UzVFp-0002cK-CT for linux-arm-kernel@lists.infradead.org; Wed, 17 Jul 2013 17:11:06 +0000 Received: by mail-pa0-f41.google.com with SMTP id bj3so2199165pad.0 for ; Wed, 17 Jul 2013 10:10:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=en+zU4NE/i/Vj6YE9wvfpX1LW5Va1E+xNdUC2jtLcEQ=; b=rDszRHxN6QrFrDkwa7ToGwaudmKlA8NL0ACIX/URv5FnQ0jdRo1thOzWMyUNVdPvVp LqQq22X5c/E4CBhOCvKtJZY3pMRX+yKN8+BWOQa8SHcENHnbkBamN3NxTNWrwcDFOKo2 zqXLvaJpTa+YQBVlaa6Ws70+DCMhPWmau6ml4dnPLMljB1oEwORCyerbttgigvQRuERE vlBfxJqkBTIWimcAotqfsvOEv/fKbnQOg294ZyDvdsKIg9Nct7EbBdnyG2zmjCLgwlkd cfCnki6RX4qnU8XRr6kT8dJV+tsXX7bxd0K0NghwpCsqhkUEyv7TqIDFlQpQOfwWCmgQ zhpA== X-Received: by 10.68.203.161 with SMTP id kr1mr7760469pbc.192.1374081043681; Wed, 17 Jul 2013 10:10:43 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id iq6sm8947632pbc.1.2013.07.17.10.10.42 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 17 Jul 2013 10:10:42 -0700 (PDT) From: Soren Brinkmann To: Michal Simek , Russell King Subject: [PATCH 2/3] arm: zynq: slcr: Clean up #defines Date: Wed, 17 Jul 2013 10:10:14 -0700 Message-Id: <1374081015-31431-3-git-send-email-soren.brinkmann@xilinx.com> X-Mailer: git-send-email 1.8.3.3 In-Reply-To: <1374081015-31431-1-git-send-email-soren.brinkmann@xilinx.com> References: <1374081015-31431-1-git-send-email-soren.brinkmann@xilinx.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130717_131105_577728_FA169239 X-CRM114-Status: GOOD ( 12.98 ) X-Spam-Score: -1.9 (-) Cc: Soren Brinkmann , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use a common naming scheme for register offset #defines: Some of those used a '_OFFSET' suffix to distinguish them from others. This scheme is used for all register offsets now. Separate the register offset #defines from others and sort them in increasing order. Signed-off-by: Soren Brinkmann --- arch/arm/mach-zynq/slcr.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 232c275..44a4ab6 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -19,17 +19,16 @@ #include #include "common.h" -#define SLCR_UNLOCK_MAGIC 0xDF0D -#define SLCR_UNLOCK 0x8 /* SCLR unlock register */ - +/* register offsets */ +#define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ +#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ +#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ +#define SLCR_UNLOCK_MAGIC 0xDF0D #define SLCR_A9_CPU_CLKSTOP 0x10 #define SLCR_A9_CPU_RST 0x1 -#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */ -#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */ - void __iomem *zynq_slcr_base; /** @@ -44,15 +43,15 @@ void zynq_slcr_system_reset(void) * Note that this seems to require raw i/o * functions or there's a lockup? */ - writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); + writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); /* * Clear 0x0F000000 bits of reboot status register to workaround * the FSBL not loading the bitstream after soft-reboot * This is a temporary solution until we know more. */ - reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS); - writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS); + reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); + writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); } @@ -64,9 +63,9 @@ void zynq_slcr_cpu_start(int cpu) { /* enable CPUn */ writel(SLCR_A9_CPU_CLKSTOP << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); + zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); /* enable CLK for CPUn */ - writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); + writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); } /** @@ -77,7 +76,7 @@ void zynq_slcr_cpu_stop(int cpu) { /* stop CLK and reset CPUn */ writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); + zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); } /** @@ -103,7 +102,7 @@ int __init zynq_slcr_init(void) } /* unlock the SLCR so that registers can be changed */ - writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); + writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);