From patchwork Wed Jul 17 23:10:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2829156 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 01243C0AB2 for ; Wed, 17 Jul 2013 23:12:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E10AF2048E for ; Wed, 17 Jul 2013 23:12:48 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 983162047D for ; Wed, 17 Jul 2013 23:12:47 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uzasn-0004xf-KA; Wed, 17 Jul 2013 23:11:42 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uzasb-0002x7-58; Wed, 17 Jul 2013 23:11:29 +0000 Received: from am1ehsobe003.messaging.microsoft.com ([213.199.154.206] helo=am1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uzas7-0002ta-Op for linux-arm-kernel@lists.infradead.org; Wed, 17 Jul 2013 23:11:02 +0000 Received: from mail48-am1-R.bigfish.com (10.3.201.235) by AM1EHSOBE017.bigfish.com (10.3.207.139) with Microsoft SMTP Server id 14.1.225.22; Wed, 17 Jul 2013 23:10:37 +0000 Received: from mail48-am1 (localhost [127.0.0.1]) by mail48-am1-R.bigfish.com (Postfix) with ESMTP id 76273300101; Wed, 17 Jul 2013 23:10:37 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz8275ch1de098h1de097h8275bhz2fh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1155h) Received-SPF: pass (mail48-am1: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail48-am1 (localhost.localdomain [127.0.0.1]) by mail48-am1 (MessageSwitch) id 1374102634922670_8372; Wed, 17 Jul 2013 23:10:34 +0000 (UTC) Received: from AM1EHSMHS021.bigfish.com (unknown [10.3.201.232]) by mail48-am1.bigfish.com (Postfix) with ESMTP id CF23980102; Wed, 17 Jul 2013 23:10:34 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by AM1EHSMHS021.bigfish.com (10.3.207.150) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 17 Jul 2013 23:10:30 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.298.1; Wed, 17 Jul 2013 16:00:00 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.121]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r6HNAMFD019802; Wed, 17 Jul 2013 16:10:28 -0700 (PDT) From: To: , Subject: [PATCH 2/4] arm: socfpga: Add platform initialization for ethernet Date: Wed, 17 Jul 2013 18:10:21 -0500 Message-ID: <1374102623-4154-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1374102623-4154-1-git-send-email-dinguyen@altera.com> References: <1374102623-4154-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130717_191100_107969_335EF124 X-CRM114-Status: GOOD ( 18.63 ) X-Spam-Score: -2.6 (--) Cc: Thomas Petazzoni , Arnd Bergmann , Pavel Machek , Jack Mitchell , Rob Herring , Olof Johansson , Dinh Nguyen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen Use the PHYLIB to set the correct clock and skew values to the Micrel PHY. Add platform specific intilization to put the STMMAC ethernet controller into the correct PHY mode. Signed-off-by: Dinh Nguyen CC: Arnd Bergmann CC: Olof Johansson Cc: Rob Herring Cc: Thomas Petazzoni Cc: Pavel Machek Cc: Jack Mitchell --- arch/arm/mach-socfpga/core.h | 8 ++++ arch/arm/mach-socfpga/socfpga.c | 85 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 92 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 572b8f7..505b8fe5 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -28,6 +28,14 @@ #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ +#define SYSMGR_EMACGRP_CTRL_OFFSET 0x60 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 + extern void socfpga_secondary_startup(void); extern void __iomem *socfpga_scu_base_addr; diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index bfce964..abbde76 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -16,10 +16,14 @@ */ #include #include +#include #include #include +#include #include #include +#include +#include #include #include @@ -33,6 +37,22 @@ void __iomem *rst_manager_base_addr; void __iomem *clk_mgr_base_addr; unsigned long cpu1start_addr; +static int stmmac_plat_init(struct platform_device *pdev); + +static struct plat_stmmacenet_data stmmacenet0_data = { + .init = &stmmac_plat_init, +}; + +static struct plat_stmmacenet_data stmmacenet1_data = { + .init = &stmmac_plat_init, +}; + +static const struct of_dev_auxdata socfpga_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff700000, NULL, &stmmacenet0_data), + OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff702000, NULL, &stmmacenet1_data), + {/* sentinel */} +}; + static struct map_desc scu_io_desc __initdata = { .virtual = SOCFPGA_SCU_VIRT_BASE, .pfn = 0, /* run-time */ @@ -58,6 +78,65 @@ static void __init socfpga_scu_map_io(void) iotable_init(&scu_io_desc, 1); } +static int ksz9021rlrn_phy_fixup(struct phy_device *phydev) +{ + if (IS_BUILTIN(CONFIG_PHYLIB)) { + /* min rx data delay */ + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000); + phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); + + /* max rx/tx clock delay, min rx/tx control delay */ + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000); + phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xa0d0); + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 0x104); + } + + return 0; +} + +static int stmmac_plat_init(struct platform_device *pdev) +{ + u32 ctrl, val, shift; + int phymode; + + if (of_machine_is_compatible("altr,socfpga-vt")) + return 0; + + phymode = of_get_phy_mode(pdev->dev.of_node); + + switch (phymode) { + case PHY_INTERFACE_MODE_RGMII: + val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + break; + default: + pr_err("%s bad phy mode %d", __func__, phymode); + return -EINVAL; + } + + if (&stmmacenet1_data == pdev->dev.platform_data) + shift = SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH; + else if (&stmmacenet0_data == pdev->dev.platform_data) + shift = 0; + else { + pr_err("%s unexpected platform data pointer\n", __func__); + return -EINVAL; + } + + ctrl = readl(sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET); + ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << shift); + ctrl |= (val << shift); + + writel(ctrl, (sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET)); + + return 0; +} + static void __init socfpga_map_io(void) { socfpga_scu_map_io(); @@ -106,9 +185,13 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) static void __init socfpga_cyclone5_init(void) { l2x0_of_init(0, ~0UL); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, + socfpga_auxdata_lookup, NULL); of_clk_init(NULL); socfpga_init_clocks(); + if (IS_BUILTIN(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_KSZ9021RLRN, + MICREL_PHY_ID_MASK, ksz9021rlrn_phy_fixup); } static const char *altera_dt_match[] = {