From patchwork Sun Jul 21 17:49:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 2830934 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CA5439F4D5 for ; Sun, 21 Jul 2013 17:50:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BC3DC2013B for ; Sun, 21 Jul 2013 17:50:16 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4CF6820136 for ; Sun, 21 Jul 2013 17:50:15 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V0xls-0004kT-LW; Sun, 21 Jul 2013 17:50:12 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V0xlq-0005FF-FR; Sun, 21 Jul 2013 17:50:10 +0000 Received: from mail-lb0-f180.google.com ([209.85.217.180]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V0xln-0005EX-5l for linux-arm-kernel@lists.infradead.org; Sun, 21 Jul 2013 17:50:08 +0000 Received: by mail-lb0-f180.google.com with SMTP id o10so4595416lbi.25 for ; Sun, 21 Jul 2013 10:49:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=eyGmRGd9YRgJJ1wGM94nnDo2ahaBKtzrdLKkTaqJ9As=; b=mYngPmYmAlpKAqBxTYi+mIq8du/usQq4ogjnbxUHqc1qQYBzdnnzPM8qOclYj6NTlv Vs0lz7066Bdo7qbMPXjq6F07jIFoKFIxlLBR+2+O2kXRI3lcgMfVuK6ClZn3QDOR/zz4 JcMaZqh9VkGU3YUeNcxGf/o+m98El8yoQILGWRhvevmgcmMdEoklU0L50yofQk+iWpXb 3u1VPy05SRL+KDHNhEqy3TXquCwzD3zwyz/Ia3xNopg1CEaxvDA4n5DhYnJS/EOsoSDw W5k7M0a5Rv8lvkzXXP6cauEjydc9rz+4t7WwuvITs7RjJZegdOdPuNgSRkcUzPRvERcr AEig== X-Received: by 10.152.25.135 with SMTP id c7mr10957235lag.39.1374428988411; Sun, 21 Jul 2013 10:49:48 -0700 (PDT) Received: from localhost.localdomain (c83-249-208-126.bredband.comhem.se. [83.249.208.126]) by mx.google.com with ESMTPSA id c4sm9686390lae.7.2013.07.21.10.49.46 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 21 Jul 2013 10:49:47 -0700 (PDT) From: Linus Walleij To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] pinctrl: elaborate a bit on arrangements in doc Date: Sun, 21 Jul 2013 19:49:40 +0200 Message-Id: <1374428980-3997-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.1.4 X-Gm-Message-State: ALoCoQk87onaO2TuHcFwyOfrNZ9jnqW1Bml5P2LlYAw9jVTNrVGO9HcEfOeoGeClydF6oHXSNCu6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130721_135007_488838_8F8B126A X-CRM114-Status: GOOD ( 21.47 ) X-Spam-Score: -2.6 (--) Cc: Anmar Oueja , Linus Walleij , Stephen Warren , Rob Landley X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This elaborates a bit on the pin control and pin muxing logic vs GPIO arangements in the hardware. Inspired by some drawings in a mail from Christian Ruppert. Both arrangements are confirmed to exist in practice. Cc: Rob Landley Reviewed-by: Christian Ruppert Signed-off-by: Linus Walleij Reviewed-by: Stephen Warren --- ChangeLog v2->v3: - Updated with lots of good input and rewording from Stephen Warren. ChangeLog v1->v2: - Cut down to two arrangements that I *know* exist in reality. - Reword, rehash, rinse, repeat... --- Documentation/pinctrl.txt | 91 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 85 insertions(+), 6 deletions(-) diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index 052e13a..d2d7fc0 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -795,18 +795,97 @@ special GPIO-handler is registered. GPIO mode pitfalls ================== -Sometime the developer may be confused by a datasheet talking about a pin -being possible to set into "GPIO mode". It appears that what hardware -engineers mean with "GPIO mode" is not necessarily the use case that is -implied in the kernel interface : a pin that you grab from -kernel code and then either listen for input or drive high/low to -assert/deassert some external line. +Due to the naming conventions used by hardware engineers, where "GPIO" +is taken to mean different things than what the kernel does, the developer +may be confused by a datasheet talking about a pin being possible to set +into "GPIO mode". It appears that what hardware engineers mean with +"GPIO mode" is not necessarily the use case that is implied in the kernel +interface : a pin that you grab from kernel code and then +either listen for input or drive high/low to assert/deassert some +external line. Rather hardware engineers think that "GPIO mode" means that you can software-control a few electrical properties of the pin that you would not be able to control if the pin was in some other mode, such as muxed in for a device. +The GPIO portions of a pin and its relation to a certain pin controller +configuration and muxing logic can be constructed in several ways. Here +are two examples: + +(A) + pin config + logic regs + | +- SPI + Physical pins --- pad --- pinmux -+- I2C + | +- mmc + | +- GPIO + pin + multiplex + logic regs + +Here some electrical properties of the pin can be configured no matter +whether the pin is used for GPIO or not. If you multiplex a GPIO onto a +pin, you can also drive it high/low from "GPIO" registers. +Alternatively, the pin can be controlled by a certain peripheral, while +still applying desired pin config properties. GPIO functionality is thus +orthogonal to any other device using the pin. + +In this arrangement the registers for the GPIO portions of the pin controller, +or the registers for the GPIO hardware module are likely to reside in a +separate memory range only intended for GPIO driving, and the register +range dealing with pin config and pin multiplexing get placed into a +different memory range and a separate section of the data sheet. + +(B) + + pin config + logic regs + | +- SPI + Physical pins --- pad --- pinmux -+- I2C + | | +- mmc + | | + GPIO pin + multiplex + logic regs + +In this arrangement, the GPIO functionality can always be enabled, such that +e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is +pulsed out. It is likely possible to disrupt the traffic on the pin by doing +wrong things on the GPIO block, as it is never really disconnected. It is +possible that the GPIO, pin config and pin multiplex registers are placed into +the same memory range and the same section of the data sheet, although that +need not be the case. + +From a kernel point of view, however, these are different aspects of the +hardware and shall be put into different subsystems: + +- Registers (or fields within registers) that control electrical + properties of the pin such as biasing and drive strength should be + exposed through the pinctrl subsystem, as "pin configuration" settings. + +- Registers (or fields within registers) that control muxing of signals + from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should + be exposed through the pinctrl subssytem, as mux functions. + +- Registers (or fields within registers) that control GPIO functionality + such as setting a GPIO's output value, reading a GPIO's input value, or + setting GPIO pin direction should be exposed through the GPIO subsystem, + and if they also support interrupt capabilities, through the irqchip + abstraction. + +Depending on the exact HW register design, some functions exposed by the +GPIO subsystem may call into the pinctrl subsystem in order to +co-ordinate register settings across HW modules. In particular, this may +be needed for HW with separate GPIO and pin controller HW modules, where +e.g. GPIO direction is determined by a register in the pin controller HW +module rather than the GPIO HW module. + +Electrical properties of the pin such as biasing and drive strength +may be placed at some pin-specific register in all cases or as part +of the GPIO register in case (B) especially. This doesn't mean that such +properties necessarily pertain to what the Linux kernel calls "GPIO". + Example: a pin is usually muxed in to be used as a UART TX line. But during system sleep, we need to put this pin into "GPIO mode" and ground it.