From patchwork Tue Jul 23 07:20:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 2831855 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 193BCC0319 for ; Tue, 23 Jul 2013 08:21:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0B264201BA for ; Tue, 23 Jul 2013 08:21:18 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A9A32018E for ; Tue, 23 Jul 2013 08:21:14 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V1X3V-00080j-It; Tue, 23 Jul 2013 07:30:46 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V1WyW-00010J-8X; Tue, 23 Jul 2013 07:25:36 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V1Wvs-0000kC-6v for linux-arm-kernel@lists.infradead.org; Tue, 23 Jul 2013 07:23:05 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r6N7MWc1005711; Tue, 23 Jul 2013 02:22:32 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r6N7MWq6026812; Tue, 23 Jul 2013 02:22:32 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Tue, 23 Jul 2013 02:22:32 -0500 Received: from sokoban.tieu.ti.com (h79-8.vpn.ti.com [172.24.79.8]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r6N7LQtu027090; Tue, 23 Jul 2013 02:22:30 -0500 From: Tero Kristo To: , , , , , , Subject: [PATCHv4 26/33] CLK: omap: gate: add support for OMAP36xx dpllx_mx_ck:s Date: Tue, 23 Jul 2013 10:20:21 +0300 Message-ID: <1374564028-11352-27-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1374564028-11352-1-git-send-email-t-kristo@ti.com> References: <1374564028-11352-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130723_032252_499501_DD38774C X-CRM114-Status: GOOD ( 12.69 ) X-Spam-Score: -8.4 (--------) Cc: devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP OMAP3630 dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset value after their respective PWRDN bits are set. Any dummy write (Any other value different from the Read value) to the corresponding CM_CLKSEL register will refresh the dividers. Signed-off-by: Tero Kristo --- drivers/clk/omap/gate.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c index b560ff4..50c7f2e 100644 --- a/drivers/clk/omap/gate.c +++ b/drivers/clk/omap/gate.c @@ -28,6 +28,10 @@ #ifdef CONFIG_OF +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) + +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk); + static const struct clk_ops omap_gate_clkdm_clk_ops = { .init = &omap2_init_clk_clkdm, .enable = &omap2_clkops_enable_clkdm, @@ -41,6 +45,54 @@ static const struct clk_ops omap_gate_clk_ops = { .is_enabled = &omap2_dflt_clk_is_enabled, }; +static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +/** + * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering + * from HSDivider PWRDN problem Implements Errata ID: i556. + * @clk: DPLL output struct clk + * + * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, + * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset + * valueafter their respective PWRDN bits are set. Any dummy write + * (Any other value different from the Read value) to the + * corresponding CM_CLKSEL register will refresh the dividers. + */ +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk) +{ + struct clk_divider *parent; + struct clk_hw *parent_hw; + u32 dummy_v, orig_v; + int ret; + + /* Clear PWRDN bit of HSDIVIDER */ + ret = omap2_dflt_clk_enable(clk); + + /* Parent is the x2 node, get parent of parent for the m2 div */ + parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk))); + parent = to_clk_divider(parent_hw); + + /* Restore the dividers */ + if (!ret) { + orig_v = __raw_readl(parent->reg); + dummy_v = orig_v; + + /* Write any other value different from the Read value */ + dummy_v ^= (1 << parent->shift); + __raw_writel(dummy_v, parent->reg); + + /* Write the original divider */ + __raw_writel(orig_v, parent->reg); + } + + return ret; +} + void __init of_omap_gate_clk_setup(struct device_node *node) { struct clk *clk; @@ -70,7 +122,10 @@ void __init of_omap_gate_clk_setup(struct device_node *node) /* No register, clkdm control only */ init.ops = &omap_gate_clkdm_clk_ops; } else { - init.ops = &omap_gate_clk_ops; + if (of_property_read_bool(node, "ti,hsdiv-restore")) + init.ops = &omap_gate_clk_hsdiv_restore_ops; + else + init.ops = &omap_gate_clk_ops; clk_hw->enable_reg = of_iomap(node, 0); of_property_read_u32(node, "ti,enable-bit", &val); clk_hw->enable_bit = val;