From patchwork Wed Jul 24 04:09:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 2832534 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 990069F4D4 for ; Wed, 24 Jul 2013 04:11:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 514FE2034F for ; Wed, 24 Jul 2013 04:11:43 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B99AB20336 for ; Wed, 24 Jul 2013 04:11:41 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V1qQ0-0001gf-SR; Wed, 24 Jul 2013 04:11:17 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V1qPo-0008UL-96; Wed, 24 Jul 2013 04:11:04 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V1qPJ-0008Pn-Iy for linux-arm-kernel@lists.infradead.org; Wed, 24 Jul 2013 04:10:36 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 23 Jul 2013 21:10:05 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 23 Jul 2013 21:09:01 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 23 Jul 2013 21:09:01 -0700 Received: from hkemhub02.nvidia.com (10.18.67.13) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.298.1; Tue, 23 Jul 2013 21:10:09 -0700 Received: from rizhao-lap.nvidia.com (10.18.67.5) by hkemhub02.nvidia.com (10.18.67.13) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 24 Jul 2013 12:10:02 +0800 From: Richard Zhao To: , , , , , , , Subject: [PATCH 1/9] ARM: dts: add generic DMA DT binding for tegra apbdma Date: Wed, 24 Jul 2013 12:09:54 +0800 Message-ID: <1374639002-16753-2-git-send-email-rizhao@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1374639002-16753-1-git-send-email-rizhao@nvidia.com> References: <1374639002-16753-1-git-send-email-rizhao@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130724_001033_940153_020BFA1E X-CRM114-Status: GOOD ( 10.11 ) X-Spam-Score: -1.9 (-) Cc: dev@lynxeye.de, swarren@wwwdotorg.org, vinod.koul@intel.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, rob.herring@calxeda.com, broonie@kernel.org, ldewangan@nvidia.com, rob@landley.net, djbw@fb.com, grant.likely@linaro.org, rizhao@nvidia.com, linuxzsc@gmail.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP All Tegra device drivers will soon move to generic DMA device tree bindings. Add the required properties to the Tegra DT files to support that. The legacy property nvidia,dma-request-selector will be removed after all drivers have been converted, in order to maintain bisectability. Changes: - Add '#dma-cells' for apbdma nodes - And properties 'dmas' and 'dma-names' for apbdma client nodes - update apbdma DT binding doc Signed-off-by: Richard Zhao --- .../devicetree/bindings/dma/tegra20-apbdma.txt | 1 + arch/arm/boot/dts/tegra114.dtsi | 27 ++++++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 27 ++++++++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 25 ++++++++++++++++++++ 4 files changed, 80 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt index 90fa7da..e4fc695 100644 --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt +++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt @@ -5,6 +5,7 @@ Required properties: - reg: Should contain DMA registers location and length. This shuld include all of the per-channel registers. - interrupts: Should contain all of the per-channel DMA interrupts. +- #dma-cells: Must be <1>, which specifies the dma request. Examples: diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index abf6c40..b133c62 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -81,6 +81,7 @@ , ; clocks = <&tegra_car TEGRA114_CLK_APBDMA>; + #dma-cells = <1>; }; ahb: ahb { @@ -125,6 +126,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 8>; + dmas = <&apbdma 8>; + dma-names = "rx-tx"; status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTA>; }; @@ -135,6 +138,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 9>; + dmas = <&apbdma 9>; + dma-names = "rx-tx"; status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTB>; }; @@ -145,6 +150,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 10>; + dmas = <&apbdma 10>; + dma-names = "rx-tx"; status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTC>; }; @@ -155,6 +162,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 19>; + dmas = <&apbdma 19>; + dma-names = "rx-tx"; status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTD>; }; @@ -227,6 +236,8 @@ reg = <0x7000d400 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 15>; + dmas = <&apbdma 15>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC1>; @@ -239,6 +250,8 @@ reg = <0x7000d600 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 16>; + dmas = <&apbdma 16>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC2>; @@ -251,6 +264,8 @@ reg = <0x7000d800 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 17>; + dmas = <&apbdma 17>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC3>; @@ -263,6 +278,8 @@ reg = <0x7000da00 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 18>; + dmas = <&apbdma 18>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC4>; @@ -275,6 +292,8 @@ reg = <0x7000dc00 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 27>; + dmas = <&apbdma 27>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC5>; @@ -287,6 +306,8 @@ reg = <0x7000de00 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 28>; + dmas = <&apbdma 28>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC6>; @@ -337,6 +358,12 @@ <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, <&apbdma 29>; + dmas = <&apbdma 1>, <&apbdma 2>, <&apbdma 3>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 7>, <&apbdma 12>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 29>; + dma-names = "channel0", "channel1", "channel2", "channel3", + "channel4", "channel5", "channel6", "channel7", + "channel8", "channel9"; clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, <&tegra_car TEGRA114_CLK_APBIF>, <&tegra_car TEGRA114_CLK_I2S0>, diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9653fd8..0fe7f37 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -182,6 +182,7 @@ , ; clocks = <&tegra_car TEGRA20_CLK_APBDMA>; + #dma-cells = <1>; }; ahb { @@ -223,6 +224,8 @@ reg = <0x70002000 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 12>; + dmas = <&apbdma 12>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA20_CLK_AC97>; status = "disabled"; }; @@ -232,6 +235,8 @@ reg = <0x70002800 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 2>; + dmas = <&apbdma 2>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA20_CLK_I2S1>; status = "disabled"; }; @@ -241,6 +246,8 @@ reg = <0x70002a00 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 1>; + dmas = <&apbdma 1>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA20_CLK_I2S2>; status = "disabled"; }; @@ -258,6 +265,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 8>; + dmas = <&apbdma 8>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA20_CLK_UARTA>; status = "disabled"; }; @@ -268,6 +277,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 9>; + dmas = <&apbdma 9>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA20_CLK_UARTB>; status = "disabled"; }; @@ -278,6 +289,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 10>; + dmas = <&apbdma 10>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA20_CLK_UARTC>; status = "disabled"; }; @@ -288,6 +301,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 19>; + dmas = <&apbdma 19>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA20_CLK_UARTD>; status = "disabled"; }; @@ -298,6 +313,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 20>; + dmas = <&apbdma 20>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA20_CLK_UARTE>; status = "disabled"; }; @@ -334,6 +351,8 @@ reg = <0x7000c380 0x80>; interrupts = ; nvidia,dma-request-selector = <&apbdma 11>; + dmas = <&apbdma 11>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SPI>; @@ -381,6 +400,8 @@ reg = <0x7000d400 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 15>; + dmas = <&apbdma 15>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC1>; @@ -392,6 +413,8 @@ reg = <0x7000d600 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 16>; + dmas = <&apbdma 16>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC2>; @@ -403,6 +426,8 @@ reg = <0x7000d800 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 17>; + dmas = <&apbdma 17>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC3>; @@ -414,6 +439,8 @@ reg = <0x7000da00 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 18>; + dmas = <&apbdma 18>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC4>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d8783f0..c266316 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -201,6 +201,7 @@ , ; clocks = <&tegra_car TEGRA30_CLK_APBDMA>; + #dma-cells = <1>; }; ahb: ahb { @@ -245,6 +246,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 8>; + dmas = <&apbdma 8>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA30_CLK_UARTA>; status = "disabled"; }; @@ -255,6 +258,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 9>; + dmas = <&apbdma 9>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA30_CLK_UARTB>; status = "disabled"; }; @@ -265,6 +270,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 10>; + dmas = <&apbdma 10>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA30_CLK_UARTC>; status = "disabled"; }; @@ -275,6 +282,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 19>; + dmas = <&apbdma 19>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA30_CLK_UARTD>; status = "disabled"; }; @@ -285,6 +294,8 @@ reg-shift = <2>; interrupts = ; nvidia,dma-request-selector = <&apbdma 20>; + dmas = <&apbdma 20>; + dma-names = "rx-tx"; clocks = <&tegra_car TEGRA30_CLK_UARTE>; status = "disabled"; }; @@ -369,6 +380,8 @@ reg = <0x7000d400 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 15>; + dmas = <&apbdma 15>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC1>; @@ -380,6 +393,8 @@ reg = <0x7000d600 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 16>; + dmas = <&apbdma 16>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC2>; @@ -391,6 +406,8 @@ reg = <0x7000d800 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 17>; + dmas = <&apbdma 17>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC3>; @@ -402,6 +419,8 @@ reg = <0x7000da00 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 18>; + dmas = <&apbdma 18>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC4>; @@ -413,6 +432,8 @@ reg = <0x7000dc00 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 27>; + dmas = <&apbdma 27>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC5>; @@ -424,6 +445,8 @@ reg = <0x7000de00 0x200>; interrupts = ; nvidia,dma-request-selector = <&apbdma 28>; + dmas = <&apbdma 28>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC6>; @@ -470,6 +493,8 @@ 0x70080200 0x100>; interrupts = ; nvidia,dma-request-selector = <&apbdma 1>; + dmas = <&apbdma 1>, <&apbdma 2>, <&apbdma 3>, <&apbdma 4>; + dma-names = "channel0", "channel1", "channel2", "channel3"; clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, <&tegra_car TEGRA30_CLK_APBIF>, <&tegra_car TEGRA30_CLK_I2S0>,