From patchwork Fri Aug 2 16:25:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 2838088 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 435D79F479 for ; Fri, 2 Aug 2013 17:16:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 56C922041C for ; Fri, 2 Aug 2013 17:16:07 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 26DBE20410 for ; Fri, 2 Aug 2013 17:16:06 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5IE5-0006ID-Fb; Fri, 02 Aug 2013 16:29:14 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5IDM-00083r-KU; Fri, 02 Aug 2013 16:28:28 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5IBu-0007pV-OB for linux-arm-kernel@lists.infradead.org; Fri, 02 Aug 2013 16:27:03 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r72GQeL6031979; Fri, 2 Aug 2013 11:26:40 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r72GQe22013633; Fri, 2 Aug 2013 11:26:40 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Fri, 2 Aug 2013 11:26:39 -0500 Received: from sokoban.tieu.ti.com (h78-17.vpn.ti.com [172.24.78.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r72GQ2Tc003114; Fri, 2 Aug 2013 11:26:38 -0500 From: Tero Kristo To: , , , , , Subject: [PATCHv5 15/31] ARM: dts: DRA7: Add PCIe related clock nodes Date: Fri, 2 Aug 2013 19:25:34 +0300 Message-ID: <1375460751-23676-16-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375460751-23676-1-git-send-email-t-kristo@ti.com> References: <1375460751-23676-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130802_122658_989321_D3ED852B X-CRM114-Status: UNSURE ( 7.99 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -8.4 (--------) Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Keerthy X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Keerthy This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk which are used by PCIe phy. It also adds a mux clock to choose the source of optfclk_pciephy_div_clk clock. Signed-off-by: Keerthy Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index eef899a..60ce28b 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -2079,3 +2079,27 @@ vip3_gclk_mux: vip3_gclk_mux@4a009030 { reg = <0x4a009030 0x4>; bit-mask = <0x1>; }; + +optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { + compatible = "divider-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x4a00821c 0x4>; + bit-mask = <0x100>; +}; + +optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { + compatible = "gate-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x4a0093b0 0x4>; + bit-shift = <9>; +}; + +optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { + compatible = "gate-clock"; + clocks = <&optfclk_pciephy_div>; + #clock-cells = <0>; + reg = <0x4a0093b0 0x4>; + bit-shift = <10>; +};