From patchwork Fri Aug 2 16:25:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 2838096 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7E05BBF535 for ; Fri, 2 Aug 2013 17:32:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D58F5201E8 for ; Fri, 2 Aug 2013 17:32:26 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BD8EC201C7 for ; Fri, 2 Aug 2013 17:32:23 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5IEP-0006gT-03; Fri, 02 Aug 2013 16:29:34 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5IDl-00086i-Nr; Fri, 02 Aug 2013 16:28:53 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5IBe-0007mQ-3E for linux-arm-kernel@lists.infradead.org; Fri, 02 Aug 2013 16:27:22 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r72GQJag030455; Fri, 2 Aug 2013 11:26:19 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r72GQJx2013327; Fri, 2 Aug 2013 11:26:19 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Fri, 2 Aug 2013 11:26:19 -0500 Received: from sokoban.tieu.ti.com (h78-17.vpn.ti.com [172.24.78.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r72GQ2TT003114; Fri, 2 Aug 2013 11:26:17 -0500 From: Tero Kristo To: , , , , , Subject: [PATCHv5 06/31] ARM: dts: omap4 clock data Date: Fri, 2 Aug 2013 19:25:25 +0300 Message-ID: <1375460751-23676-7-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375460751-23676-1-git-send-email-t-kristo@ti.com> References: <1375460751-23676-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130802_122642_578884_3797895F X-CRM114-Status: GOOD ( 11.00 ) X-Spam-Score: -8.4 (--------) Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch creates a unique node for each clock in the OMAP4 power, reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly different clock tree which is taken into account in the data. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap443x-clocks.dtsi | 17 + arch/arm/boot/dts/omap443x.dtsi | 8 + arch/arm/boot/dts/omap4460.dtsi | 8 + arch/arm/boot/dts/omap446x-clocks.dtsi | 27 + arch/arm/boot/dts/omap44xx-clocks.dtsi | 1648 ++++++++++++++++++++++++++++++++ 5 files changed, 1708 insertions(+) create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi new file mode 100644 index 0000000..2bd82b2 --- /dev/null +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi @@ -0,0 +1,17 @@ +/* + * Device Tree Source for OMAP443x clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +bandgap_fclk: bandgap_fclk@4a307888 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_32k_ck>; + bit-shift = <8>; + reg = <0x4a307888 0x4>; +}; diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index bcf455e..dfd648c 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi @@ -30,4 +30,12 @@ 0x4a00232C 0x4>; compatible = "ti,omap4430-bandgap"; }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /include/ "omap44xx-clocks.dtsi" + /include/ "omap443x-clocks.dtsi" + }; }; diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index c2f0f39..d9d00b2 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi @@ -38,4 +38,12 @@ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ gpios = <&gpio3 22 0>; /* tshut */ }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /include/ "omap44xx-clocks.dtsi" + /include/ "omap446x-clocks.dtsi" + }; }; diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi new file mode 100644 index 0000000..86d0805 --- /dev/null +++ b/arch/arm/boot/dts/omap446x-clocks.dtsi @@ -0,0 +1,27 @@ +/* + * Device Tree Source for OMAP446x clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +div_ts_ck: div_ts_ck@4a307888 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + bit-shift = <24>; + reg = <0x4a307888 0x4>; + table = < 8 0 >, < 16 1 >, < 32 2 >; + bit-mask = <0x3>; +}; + +bandgap_ts_fclk: bandgap_ts_fclk@4a307888 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&div_ts_ck>; + bit-shift = <8>; + reg = <0x4a307888 0x4>; +}; diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi new file mode 100644 index 0000000..23f623c --- /dev/null +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -0,0 +1,1648 @@ +/* + * Device Tree Source for OMAP4 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +extalt_clkin_ck: extalt_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <59000000>; +}; + +pad_clks_src_ck: pad_clks_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; +}; + +pad_clks_ck: pad_clks_ck@4a004108 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&pad_clks_src_ck>; + bit-shift = <8>; + reg = <0x4a004108 0x4>; +}; + +pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; +}; + +secure_32k_clk_src_ck: secure_32k_clk_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; +}; + +slimbus_src_clk: slimbus_src_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; +}; + +slimbus_clk: slimbus_clk@4a004108 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&slimbus_src_clk>; + bit-shift = <10>; + reg = <0x4a004108 0x4>; +}; + +sys_32k_ck: sys_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; +}; + +virt_12000000_ck: virt_12000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; +}; + +virt_13000000_ck: virt_13000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; +}; + +virt_16800000_ck: virt_16800000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16800000>; +}; + +virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; +}; + +virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; +}; + +virt_27000000_ck: virt_27000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; +}; + +virt_38400000_ck: virt_38400000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <38400000>; +}; + +sys_clkin_ck: sys_clkin_ck@4a306110 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; + reg = <0x4a306110 0x4>; + bit-mask = <0x7>; + index-starts-at-one; +}; + +tie_low_clock_ck: tie_low_clock_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; +}; + +utmi_phy_clkout_ck: utmi_phy_clkout_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; +}; + +xclk60mhsp1_ck: xclk60mhsp1_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; +}; + +xclk60mhsp2_ck: xclk60mhsp2_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; +}; + +xclk60motg_ck: xclk60motg_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; +}; + +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a306108 0x4>; + bit-mask = <0x1>; +}; + +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + reg = <0x4a30610c 0x4>; + bit-mask = <0x1>; +}; + +dpll_abe_ck: dpll_abe_ck@4a0041e0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-m4xen-clock"; + clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; + reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>; + ti,clk-ref = <&abe_dpll_refclk_mux_ck>; + ti,clk-bypass = <&abe_dpll_bypass_clk_mux_ck>; +}; + +dpll_abe_x2_ck: dpll_abe_x2_ck@4a0041f0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_abe_ck>; + reg = <0x4a0041f0 0x4>; +}; + +dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a0041f0 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +abe_24m_fclk: abe_24m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <8>; +}; + +abe_clk: abe_clk@4a004108 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_abe_m2x2_ck>; + reg = <0x4a004108 0x4>; + bit-mask = <0x3>; + index-power-of-two; +}; + +aess_fclk: aess_fclk@4a004528 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&abe_clk>; + bit-shift = <24>; + reg = <0x4a004528 0x4>; + bit-mask = <0x1>; +}; + +dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a0041f4 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@4a00412c { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; + bit-shift = <23>; + reg = <0x4a00412c 0x4>; + bit-mask = <0x1>; +}; + +dpll_core_ck: dpll_core_ck@4a004120 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-core-clock"; + clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; + reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>; + ti,clk-ref = <&sys_clkin_ck>; + ti,clk-bypass = <&core_hsd_byp_clk_mux_ck>; +}; + +dpll_core_x2_ck: dpll_core_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_core_ck>; +}; + +dpll_core_m6x2_ck: dpll_core_m6x2_ck@4a004140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a004140 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +dbgclk_mux_ck: dbgclk_mux_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; +}; + +dpll_core_m2_ck: dpll_core_m2_ck@4a004130 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a004130 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +ddrphy_ck: ddrphy_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m2_ck>; + clock-mult = <1>; + clock-div = <2>; +}; + +dpll_core_m5x2_ck: dpll_core_m5x2_ck@4a00413c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a00413c 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +div_core_ck: div_core_ck@4a004100 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_core_m5x2_ck>; + reg = <0x4a004100 0x4>; + bit-mask = <0x1>; +}; + +div_iva_hs_clk: div_iva_hs_clk@4a0041dc { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_core_m5x2_ck>; + reg = <0x4a0041dc 0x4>; + bit-mask = <0x3>; + index-power-of-two; +}; + +div_mpu_hs_clk: div_mpu_hs_clk@4a00419c { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_core_m5x2_ck>; + reg = <0x4a00419c 0x4>; + bit-mask = <0x3>; + index-power-of-two; +}; + +dpll_core_m4x2_ck: dpll_core_m4x2_ck@4a004138 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a004138 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +dll_clk_div_ck: dll_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4x2_ck>; + clock-mult = <1>; + clock-div = <2>; +}; + +dpll_abe_m2_ck: dpll_abe_m2_ck@4a0041f0 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_abe_ck>; + reg = <0x4a0041f0 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; +}; + +dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@4a004134 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_core_x2_ck>; + reg = <0x4a004134 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; +}; + +dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_core_m3x2_div_ck>; + bit-shift = <8>; + reg = <0x4a004134 0x4>; +}; + +dpll_core_m7x2_ck: dpll_core_m7x2_ck@4a004144 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a004144 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@4a0041ac { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; + bit-shift = <23>; + reg = <0x4a0041ac 0x4>; + bit-mask = <0x1>; +}; + +dpll_iva_ck: dpll_iva_ck@4a0041a0 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; + reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>; + ti,clk-ref = <&sys_clkin_ck>; + ti,clk-bypass = <&iva_hsd_byp_clk_mux_ck>; +}; + +dpll_iva_x2_ck: dpll_iva_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_iva_ck>; +}; + +dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@4a0041b8 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_iva_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a0041b8 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@4a0041bc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_iva_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a0041bc 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +dpll_mpu_ck: dpll_mpu_ck@4a004160 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; + reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>; + ti,clk-ref = <&sys_clkin_ck>; + ti,clk-bypass = <&div_mpu_hs_clk>; +}; + +dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_mpu_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a004170 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +per_hs_clk_div_ck: per_hs_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <2>; +}; + +per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@4a00814c { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; + bit-shift = <23>; + reg = <0x4a00814c 0x4>; + bit-mask = <0x1>; +}; + +dpll_per_ck: dpll_per_ck@4a008140 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; + reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>; + ti,clk-ref = <&sys_clkin_ck>; + ti,clk-bypass = <&per_hsd_byp_clk_mux_ck>; +}; + +dpll_per_m2_ck: dpll_per_m2_ck@4a008150 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_per_ck>; + reg = <0x4a008150 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; +}; + +dpll_per_x2_ck: dpll_per_x2_ck@4a008150 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_per_ck>; + reg = <0x4a008150 0x4>; +}; + +dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a008150 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@4a008154 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_per_x2_ck>; + reg = <0x4a008154 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; +}; + +dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m3x2_div_ck>; + bit-shift = <8>; + reg = <0x4a008154 0x4>; +}; + +dpll_per_m4x2_ck: dpll_per_m4x2_ck@4a008158 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a008158 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +dpll_per_m5x2_ck: dpll_per_m5x2_ck@4a00815c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a00815c 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +dpll_per_m6x2_ck: dpll_per_m6x2_ck@4a008160 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a008160 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +dpll_per_m7x2_ck: dpll_per_m7x2_ck@4a008164 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a008164 0x4>; + bit-mask = <0x1f>; + index-starts-at-one; + ti,autoidle-low; +}; + +usb_hs_clk_div_ck: usb_hs_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <3>; +}; + +dpll_usb_ck: dpll_usb_ck@4a008180 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-j-type-clock"; + clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; + ti,clk-bypass = <&usb_hs_clk_div_ck>; + reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>; + ti,clk-ref = <&sys_clkin_ck>; + ti,clkdm-name = "l3_init_clkdm"; + ti,dpll-j-type; +}; + +dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@4a0081b4 { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&dpll_usb_ck>; + ti,autoidle-shift = <8>; + clock-div = <1>; + reg = <0x4a0081b4 0x4>; + clock-mult = <1>; + ti,autoidle-low; +}; + +dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_ck>; + ti,autoidle-shift = <8>; + reg = <0x4a008190 0x4>; + bit-mask = <0x7f>; + index-starts-at-one; + ti,autoidle-low; +}; + +ducati_clk_mux_ck: ducati_clk_mux_ck@4a008100 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; + reg = <0x4a008100 0x4>; + bit-mask = <0x1>; +}; + +func_12m_fclk: func_12m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; +}; + +func_24m_clk: func_24m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; +}; + +func_24mc_fclk: func_24mc_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <8>; +}; + +func_48m_fclk: func_48m_fclk@4a008108 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_per_m2x2_ck>; + reg = <0x4a008108 0x4>; + table = < 4 0 >, < 8 1 >; + bit-mask = <0x1>; +}; + +func_48mc_fclk: func_48mc_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <4>; +}; + +func_64m_fclk: func_64m_fclk@4a008108 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_per_m4x2_ck>; + reg = <0x4a008108 0x4>; + table = < 2 0 >, < 4 1 >; + bit-mask = <0x1>; +}; + +func_96m_fclk: func_96m_fclk@4a008108 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_per_m2x2_ck>; + reg = <0x4a008108 0x4>; + table = < 2 0 >, < 4 1 >; + bit-mask = <0x1>; +}; + +init_60m_fclk: init_60m_fclk@4a008104 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_usb_m2_ck>; + reg = <0x4a008104 0x4>; + table = < 1 0 >, < 8 1 >; + bit-mask = <0x1>; +}; + +l3_div_ck: l3_div_ck@4a004100 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&div_core_ck>; + bit-shift = <4>; + reg = <0x4a004100 0x4>; + bit-mask = <0x1>; +}; + +l4_div_ck: l4_div_ck@4a004100 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&l3_div_ck>; + bit-shift = <8>; + reg = <0x4a004100 0x4>; + bit-mask = <0x1>; +}; + +lp_clk_div_ck: lp_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; +}; + +l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@4a306108 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; + reg = <0x4a306108 0x4>; + bit-mask = <0x1>; +}; + +mpu_periphclk: mpu_periphclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_mpu_ck>; + clock-mult = <1>; + clock-div = <2>; +}; + +ocp_abe_iclk: ocp_abe_iclk@4a004528 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&aess_fclk>; + bit-shift = <24>; + reg = <0x4a004528 0x4>; + table = < 2 0 >, < 1 1 >; + bit-mask = <0x1>; +}; + +per_abe_24m_fclk: per_abe_24m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m2_ck>; + clock-mult = <1>; + clock-div = <4>; +}; + +per_abe_nc_fclk: per_abe_nc_fclk@4a008108 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_abe_m2_ck>; + reg = <0x4a008108 0x4>; + bit-mask = <0x1>; +}; + +syc_clk_div_ck: syc_clk_div_ck@4a306100 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&sys_clkin_ck>; + reg = <0x4a306100 0x4>; + bit-mask = <0x1>; +}; + +aes1_fck: aes1_fck@4a0095a0 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&l3_div_ck>; + bit-shift = <1>; + reg = <0x4a0095a0 0x4>; +}; + +aes2_fck: aes2_fck@4a0095a8 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&l3_div_ck>; + bit-shift = <1>; + reg = <0x4a0095a8 0x4>; +}; + +dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + bit-shift = <25>; + reg = <0x4a004538 0x4>; + bit-mask = <0x1>; +}; + +func_dmic_abe_gfclk: func_dmic_abe_gfclk@4a004538 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + bit-shift = <24>; + reg = <0x4a004538 0x4>; + bit-mask = <0x3>; +}; + +dss_sys_clk: dss_sys_clk@4a009120 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&syc_clk_div_ck>; + bit-shift = <10>; + reg = <0x4a009120 0x4>; +}; + +dss_tv_clk: dss_tv_clk@4a009120 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&extalt_clkin_ck>; + bit-shift = <11>; + reg = <0x4a009120 0x4>; +}; + +dss_dss_clk: dss_dss_clk@4a009120 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m5x2_ck>; + bit-shift = <8>; + reg = <0x4a009120 0x4>; +}; + +dss_48mhz_clk: dss_48mhz_clk@4a009120 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&func_48mc_fclk>; + bit-shift = <9>; + reg = <0x4a009120 0x4>; +}; + +dss_fck: dss_fck@4a009120 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&l3_div_ck>; + bit-shift = <1>; + reg = <0x4a009120 0x4>; +}; + +fdif_fck: fdif_fck@4a009028 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_per_m4x2_ck>; + bit-shift = <24>; + reg = <0x4a009028 0x4>; + bit-mask = <0x3>; + index-power-of-two; +}; + +gpio1_dbclk: gpio1_dbclk@4a307838 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_32k_ck>; + bit-shift = <8>; + reg = <0x4a307838 0x4>; +}; + +gpio2_dbclk: gpio2_dbclk@4a009460 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_32k_ck>; + bit-shift = <8>; + reg = <0x4a009460 0x4>; +}; + +gpio3_dbclk: gpio3_dbclk@4a009468 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_32k_ck>; + bit-shift = <8>; + reg = <0x4a009468 0x4>; +}; + +gpio4_dbclk: gpio4_dbclk@4a009470 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_32k_ck>; + bit-shift = <8>; + reg = <0x4a009470 0x4>; +}; + +gpio5_dbclk: gpio5_dbclk@4a009478 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_32k_ck>; + bit-shift = <8>; + reg = <0x4a009478 0x4>; +}; + +gpio6_dbclk: gpio6_dbclk@4a009480 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_32k_ck>; + bit-shift = <8>; + reg = <0x4a009480 0x4>; +}; + +sgx_clk_mux: sgx_clk_mux@4a009220 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>; + bit-shift = <24>; + reg = <0x4a009220 0x4>; + bit-mask = <0x1>; +}; + +hsi_fck: hsi_fck@4a009338 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_per_m2x2_ck>; + bit-shift = <24>; + reg = <0x4a009338 0x4>; + bit-mask = <0x3>; + index-power-of-two; +}; + +iss_ctrlclk: iss_ctrlclk@4a009020 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&func_96m_fclk>; + bit-shift = <8>; + reg = <0x4a009020 0x4>; +}; + +mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + bit-shift = <25>; + reg = <0x4a004540 0x4>; + bit-mask = <0x1>; +}; + +func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@4a004540 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + bit-shift = <24>; + reg = <0x4a004540 0x4>; + bit-mask = <0x3>; +}; + +mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + bit-shift = <25>; + reg = <0x4a004548 0x4>; + bit-mask = <0x1>; +}; + +func_mcbsp1_gfclk: func_mcbsp1_gfclk@4a004548 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + bit-shift = <24>; + reg = <0x4a004548 0x4>; + bit-mask = <0x3>; +}; + +mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + bit-shift = <25>; + reg = <0x4a004550 0x4>; + bit-mask = <0x1>; +}; + +func_mcbsp2_gfclk: func_mcbsp2_gfclk@4a004550 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + bit-shift = <24>; + reg = <0x4a004550 0x4>; + bit-mask = <0x3>; +}; + +mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + bit-shift = <25>; + reg = <0x4a004558 0x4>; + bit-mask = <0x1>; +}; + +func_mcbsp3_gfclk: func_mcbsp3_gfclk@4a004558 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + bit-shift = <24>; + reg = <0x4a004558 0x4>; + bit-mask = <0x3>; +}; + +mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@4a0094e0 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>; + bit-shift = <25>; + reg = <0x4a0094e0 0x4>; + bit-mask = <0x1>; +}; + +per_mcbsp4_gfclk: per_mcbsp4_gfclk@4a0094e0 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>; + bit-shift = <24>; + reg = <0x4a0094e0 0x4>; + bit-mask = <0x1>; +}; + +hsmmc1_fclk: hsmmc1_fclk@4a009328 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&func_64m_fclk>, <&func_96m_fclk>; + bit-shift = <24>; + reg = <0x4a009328 0x4>; + bit-mask = <0x1>; +}; + +hsmmc2_fclk: hsmmc2_fclk@4a009330 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&func_64m_fclk>, <&func_96m_fclk>; + bit-shift = <24>; + reg = <0x4a009330 0x4>; + bit-mask = <0x1>; +}; + +ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@4a0093e0 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&func_48m_fclk>; + bit-shift = <8>; + reg = <0x4a0093e0 0x4>; +}; + +sha2md5_fck: sha2md5_fck@4a0095c8 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&l3_div_ck>; + bit-shift = <1>; + reg = <0x4a0095c8 0x4>; +}; + +slimbus1_fclk_1: slimbus1_fclk_1@4a004560 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&func_24m_clk>; + bit-shift = <9>; + reg = <0x4a004560 0x4>; +}; + +slimbus1_fclk_0: slimbus1_fclk_0@4a004560 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&abe_24m_fclk>; + bit-shift = <8>; + reg = <0x4a004560 0x4>; +}; + +slimbus1_fclk_2: slimbus1_fclk_2@4a004560 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&pad_clks_ck>; + bit-shift = <10>; + reg = <0x4a004560 0x4>; +}; + +slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&slimbus_clk>; + bit-shift = <11>; + reg = <0x4a004560 0x4>; +}; + +slimbus2_fclk_1: slimbus2_fclk_1@4a009538 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&per_abe_24m_fclk>; + bit-shift = <9>; + reg = <0x4a009538 0x4>; +}; + +slimbus2_fclk_0: slimbus2_fclk_0@4a009538 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&func_24mc_fclk>; + bit-shift = <8>; + reg = <0x4a009538 0x4>; +}; + +slimbus2_slimbus_clk: slimbus2_slimbus_clk@4a009538 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&pad_slimbus_core_clks_ck>; + bit-shift = <10>; + reg = <0x4a009538 0x4>; +}; + +smartreflex_core_fck: smartreflex_core_fck@4a008638 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + bit-shift = <1>; + reg = <0x4a008638 0x4>; +}; + +smartreflex_iva_fck: smartreflex_iva_fck@4a008630 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + bit-shift = <1>; + reg = <0x4a008630 0x4>; +}; + +smartreflex_mpu_fck: smartreflex_mpu_fck@4a008628 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + bit-shift = <1>; + reg = <0x4a008628 0x4>; +}; + +dmt1_clk_mux: dmt1_clk_mux@4a307840 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a307840 0x4>; + bit-mask = <0x1>; +}; + +cm2_dm10_mux: cm2_dm10_mux@4a009428 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a009428 0x4>; + bit-mask = <0x1>; +}; + +cm2_dm11_mux: cm2_dm11_mux@4a009430 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a009430 0x4>; + bit-mask = <0x1>; +}; + +cm2_dm2_mux: cm2_dm2_mux@4a009438 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a009438 0x4>; + bit-mask = <0x1>; +}; + +cm2_dm3_mux: cm2_dm3_mux@4a009440 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a009440 0x4>; + bit-mask = <0x1>; +}; + +cm2_dm4_mux: cm2_dm4_mux@4a009448 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a009448 0x4>; + bit-mask = <0x1>; +}; + +timer5_sync_mux: timer5_sync_mux@4a004568 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a004568 0x4>; + bit-mask = <0x1>; +}; + +timer6_sync_mux: timer6_sync_mux@4a004570 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a004570 0x4>; + bit-mask = <0x1>; +}; + +timer7_sync_mux: timer7_sync_mux@4a004578 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a004578 0x4>; + bit-mask = <0x1>; +}; + +timer8_sync_mux: timer8_sync_mux@4a004580 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a004580 0x4>; + bit-mask = <0x1>; +}; + +cm2_dm9_mux: cm2_dm9_mux@4a009450 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + bit-shift = <24>; + reg = <0x4a009450 0x4>; + bit-mask = <0x1>; +}; + +usb_host_fs_fck: usb_host_fs_fck@4a0093d0 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&func_48mc_fclk>; + reg = <0x4a0093d0 0x4>; + bit-shift = <1>; +}; + +utmi_p1_gfclk: utmi_p1_gfclk@4a009358 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>; + bit-shift = <24>; + reg = <0x4a009358 0x4>; + bit-mask = <0x1>; +}; + +usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009358 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&utmi_p1_gfclk>; + bit-shift = <8>; + reg = <0x4a009358 0x4>; +}; + +utmi_p2_gfclk: utmi_p2_gfclk@4a009358 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>; + bit-shift = <25>; + reg = <0x4a009358 0x4>; + bit-mask = <0x1>; +}; + +usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009358 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&utmi_p2_gfclk>; + bit-shift = <9>; + reg = <0x4a009358 0x4>; +}; + +usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009358 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&init_60m_fclk>; + bit-shift = <10>; + reg = <0x4a009358 0x4>; +}; + +usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009358 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_usb_m2_ck>; + bit-shift = <13>; + reg = <0x4a009358 0x4>; +}; + +usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009358 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&init_60m_fclk>; + bit-shift = <11>; + reg = <0x4a009358 0x4>; +}; + +usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009358 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&init_60m_fclk>; + bit-shift = <12>; + reg = <0x4a009358 0x4>; +}; + +usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009358 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_usb_m2_ck>; + bit-shift = <14>; + reg = <0x4a009358 0x4>; +}; + +usb_host_hs_func48mclk: usb_host_hs_func48mclk@4a009358 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&func_48mc_fclk>; + bit-shift = <15>; + reg = <0x4a009358 0x4>; +}; + +usb_host_hs_fck: usb_host_hs_fck@4a009358 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&init_60m_fclk>; + bit-shift = <1>; + reg = <0x4a009358 0x4>; +}; + +otg_60m_gfclk: otg_60m_gfclk@4a009360 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>; + bit-shift = <24>; + reg = <0x4a009360 0x4>; + bit-mask = <0x1>; +}; + +usb_otg_hs_xclk: usb_otg_hs_xclk@4a009360 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&otg_60m_gfclk>; + bit-shift = <8>; + reg = <0x4a009360 0x4>; +}; + +usb_otg_hs_ick: usb_otg_hs_ick@4a009360 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&l3_div_ck>; + bit-shift = <0>; + reg = <0x4a009360 0x4>; +}; + +usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_32k_ck>; + bit-shift = <8>; + reg = <0x4a008640 0x4>; +}; + +usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009368 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&init_60m_fclk>; + bit-shift = <10>; + reg = <0x4a009368 0x4>; +}; + +usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009368 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&init_60m_fclk>; + bit-shift = <8>; + reg = <0x4a009368 0x4>; +}; + +usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009368 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&init_60m_fclk>; + bit-shift = <9>; + reg = <0x4a009368 0x4>; +}; + +usb_tll_hs_ick: usb_tll_hs_ick@4a009368 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&l4_div_ck>; + bit-shift = <0>; + reg = <0x4a009368 0x4>; +}; + +usim_ck: usim_ck@4a307858 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&dpll_per_m4x2_ck>; + bit-shift = <24>; + reg = <0x4a307858 0x4>; + table = < 14 0 >, < 18 1 >; + bit-mask = <0x1>; +}; + +usim_fclk: usim_fclk@4a307858 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&usim_ck>; + bit-shift = <8>; + reg = <0x4a307858 0x4>; +}; + +pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@4a307a20 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; + bit-shift = <20>; + reg = <0x4a307a20 0x4>; + bit-mask = <0x3>; +}; + +pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@4a307a20 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; + bit-shift = <22>; + reg = <0x4a307a20 0x4>; + bit-mask = <0x3>; +}; + +stm_clk_div_ck: stm_clk_div_ck@4a307a20 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&pmd_stm_clock_mux_ck>; + bit-shift = <27>; + reg = <0x4a307a20 0x4>; + bit-mask = <0x7>; + index-power-of-two; +}; + +trace_clk_div_div_ck: trace_clk_div_div_ck@4a307a20 { + #clock-cells = <0>; + compatible = "divider-clock"; + bit-shift = <24>; + reg = <0x4a307a20 0x4>; + bit-mask = <0x7>; + index-power-of-two; +}; + +trace_clk_div_ck: trace_clk_div_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&trace_clk_div_div_ck>; + ti,clkdm-name = "emu_sys_clkdm"; +}; + +auxclk0_src_mux_ck: auxclk0_src_mux_ck@4a30a310 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + bit-shift = <1>; + reg = <0x4a30a310 0x4>; + bit-mask = <0x3>; +}; + +auxclk0_src_ck: auxclk0_src_ck@4a30a310 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&auxclk0_src_mux_ck>; + bit-shift = <8>; + reg = <0x4a30a310 0x4>; +}; + +auxclk0_ck: auxclk0_ck@4a30a310 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&auxclk0_src_ck>; + bit-shift = <16>; + reg = <0x4a30a310 0x4>; + bit-mask = <0xf>; +}; + +auxclk1_src_mux_ck: auxclk1_src_mux_ck@4a30a314 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + bit-shift = <1>; + reg = <0x4a30a314 0x4>; + bit-mask = <0x3>; +}; + +auxclk1_src_ck: auxclk1_src_ck@4a30a314 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&auxclk1_src_mux_ck>; + bit-shift = <8>; + reg = <0x4a30a314 0x4>; +}; + +auxclk1_ck: auxclk1_ck@4a30a314 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&auxclk1_src_ck>; + bit-shift = <16>; + reg = <0x4a30a314 0x4>; + bit-mask = <0xf>; +}; + +auxclk2_src_mux_ck: auxclk2_src_mux_ck@4a30a318 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + bit-shift = <1>; + reg = <0x4a30a318 0x4>; + bit-mask = <0x3>; +}; + +auxclk2_src_ck: auxclk2_src_ck@4a30a318 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&auxclk2_src_mux_ck>; + bit-shift = <8>; + reg = <0x4a30a318 0x4>; +}; + +auxclk2_ck: auxclk2_ck@4a30a318 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&auxclk2_src_ck>; + bit-shift = <16>; + reg = <0x4a30a318 0x4>; + bit-mask = <0xf>; +}; + +auxclk3_src_mux_ck: auxclk3_src_mux_ck@4a30a31c { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + bit-shift = <1>; + reg = <0x4a30a31c 0x4>; + bit-mask = <0x3>; +}; + +auxclk3_src_ck: auxclk3_src_ck@4a30a31c { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&auxclk3_src_mux_ck>; + bit-shift = <8>; + reg = <0x4a30a31c 0x4>; +}; + +auxclk3_ck: auxclk3_ck@4a30a31c { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&auxclk3_src_ck>; + bit-shift = <16>; + reg = <0x4a30a31c 0x4>; + bit-mask = <0xf>; +}; + +auxclk4_src_mux_ck: auxclk4_src_mux_ck@4a30a320 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + bit-shift = <1>; + reg = <0x4a30a320 0x4>; + bit-mask = <0x3>; +}; + +auxclk4_src_ck: auxclk4_src_ck@4a30a320 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&auxclk4_src_mux_ck>; + bit-shift = <8>; + reg = <0x4a30a320 0x4>; +}; + +auxclk4_ck: auxclk4_ck@4a30a320 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&auxclk4_src_ck>; + bit-shift = <16>; + reg = <0x4a30a320 0x4>; + bit-mask = <0xf>; +}; + +auxclk5_src_mux_ck: auxclk5_src_mux_ck@4a30a324 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + bit-shift = <1>; + reg = <0x4a30a324 0x4>; + bit-mask = <0x3>; +}; + +auxclk5_src_ck: auxclk5_src_ck@4a30a324 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&auxclk5_src_mux_ck>; + bit-shift = <8>; + reg = <0x4a30a324 0x4>; +}; + +auxclk5_ck: auxclk5_ck@4a30a324 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&auxclk5_src_ck>; + bit-shift = <16>; + reg = <0x4a30a324 0x4>; + bit-mask = <0xf>; +}; + +auxclkreq0_ck: auxclkreq0_ck@4a30a210 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + bit-shift = <2>; + reg = <0x4a30a210 0x4>; + bit-mask = <0x7>; +}; + +auxclkreq1_ck: auxclkreq1_ck@4a30a214 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + bit-shift = <2>; + reg = <0x4a30a214 0x4>; + bit-mask = <0x7>; +}; + +auxclkreq2_ck: auxclkreq2_ck@4a30a218 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + bit-shift = <2>; + reg = <0x4a30a218 0x4>; + bit-mask = <0x7>; +}; + +auxclkreq3_ck: auxclkreq3_ck@4a30a21c { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + bit-shift = <2>; + reg = <0x4a30a21c 0x4>; + bit-mask = <0x7>; +}; + +auxclkreq4_ck: auxclkreq4_ck@4a30a220 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + bit-shift = <2>; + reg = <0x4a30a220 0x4>; + bit-mask = <0x7>; +}; + +auxclkreq5_ck: auxclkreq5_ck@4a30a224 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + bit-shift = <2>; + reg = <0x4a30a224 0x4>; + bit-mask = <0x7>; +};