From patchwork Sun Aug 4 13:39:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 2838410 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1BD35BF535 for ; Sun, 4 Aug 2013 13:39:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1D1DA20171 for ; Sun, 4 Aug 2013 13:39:17 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0E59F20170 for ; Sun, 4 Aug 2013 13:39:16 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5yWe-0006L5-EX; Sun, 04 Aug 2013 13:39:12 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5yWc-0000eS-DZ; Sun, 04 Aug 2013 13:39:10 +0000 Received: from co9ehsobe002.messaging.microsoft.com ([207.46.163.25] helo=co9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5yWZ-0000e6-Ta for linux-arm-kernel@lists.infradead.org; Sun, 04 Aug 2013 13:39:08 +0000 Received: from mail128-co9-R.bigfish.com (10.236.132.238) by CO9EHSOBE003.bigfish.com (10.236.130.66) with Microsoft SMTP Server id 14.1.225.22; Sun, 4 Aug 2013 13:38:38 +0000 Received: from mail128-co9 (localhost [127.0.0.1]) by mail128-co9-R.bigfish.com (Postfix) with ESMTP id 9E7E4B600F1; Sun, 4 Aug 2013 13:38:38 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh8275dh1de097hz2dh87h2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1151h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail128-co9 (localhost.localdomain [127.0.0.1]) by mail128-co9 (MessageSwitch) id 1375623516496929_9576; Sun, 4 Aug 2013 13:38:36 +0000 (UTC) Received: from CO9EHSMHS010.bigfish.com (unknown [10.236.132.247]) by mail128-co9.bigfish.com (Postfix) with ESMTP id 6AF0854004B; Sun, 4 Aug 2013 13:38:36 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS010.bigfish.com (10.236.130.20) with Microsoft SMTP Server (TLS) id 14.16.227.3; Sun, 4 Aug 2013 13:38:31 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.136.1; Sun, 4 Aug 2013 13:38:30 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.26]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r74DcR08022737; Sun, 4 Aug 2013 06:38:28 -0700 From: Shawn Guo To: Linus Walleij Subject: [PATCH v2] pinctrl: imx: work around select input quirk Date: Sun, 4 Aug 2013 21:39:23 +0800 Message-ID: <1375623563-23706-1-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130804_093908_115400_5761E2A0 X-CRM114-Status: GOOD ( 16.91 ) X-Spam-Score: -4.2 (----) Cc: linux-arm-kernel@lists.infradead.org, Shawn Guo , Peter Chen , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The select input for some pin may not be implemented using the regular select input register but the general purpose register. A real example is that imx6q designers found the select input for USB OTG ID pin is missing at the very late stage, and can not add a new select input register but have to use a general purpose register bit to implement it. The patch adds a workaround for such select input quirk by interpreting the input_val cell of pin function ID in a different way, so that all the info that needed for setting up select input bits in general purpose register could be decoded from there. Signed-off-by: Shawn Guo Tested-by: Peter Chen --- Changes since v1: * For quirky select input where IOMUXC general purpose register is used, the register could be possibly at offset 0. Cover this case in v2. drivers/pinctrl/pinctrl-imx.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c index 57a4eb0..7284b86 100644 --- a/drivers/pinctrl/pinctrl-imx.c +++ b/drivers/pinctrl/pinctrl-imx.c @@ -239,8 +239,38 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", pin_reg->mux_reg, mux[i]); - /* some pins also need select input setting, set it if found */ - if (input_reg[i]) { + /* + * If the select input value begins with 0xff, it's a quirky + * select input and the value should be interpreted as below. + * 31 23 15 7 0 + * | 0xff | shift | width | select | + * It's used to work around the problem that the select + * input for some pin is not implemented in the select + * input register but in some general purpose register. + * We encode the select input value, width and shift of + * the bit field into input_val cell of pin function ID + * in device tree, and then decode them here for setting + * up the select input bits in general purpose register. + */ + if (input_val[i] >> 24 == 0xff) { + u32 val = input_val[i]; + u8 select = val & 0xff; + u8 width = (val >> 8) & 0xff; + u8 shift = (val >> 16) & 0xff; + u32 mask = ((1 << width) - 1) << shift; + /* + * The input_reg[i] here is actually some IOMUXC general + * purpose register, not regular select input register. + */ + val = readl(ipctl->base + input_reg[i]); + val &= ~mask; + val |= select << shift; + writel(val, ipctl->base + input_reg[i]); + } else if (input_reg[i]) { + /* + * Regular select input register can never be at offset + * 0, and we only print register value for regular case. + */ writel(input_val[i], ipctl->base + input_reg[i]); dev_dbg(ipctl->dev, "==>select_input: offset 0x%x val 0x%x\n",