From patchwork Mon Aug 5 11:20:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 2838652 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7E7B1BF535 for ; Mon, 5 Aug 2013 12:12:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CF0182015B for ; Mon, 5 Aug 2013 12:12:31 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 747F320149 for ; Mon, 5 Aug 2013 12:12:30 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V6IsY-0005Z3-6f; Mon, 05 Aug 2013 11:23:11 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V6Irv-0002vL-5j; Mon, 05 Aug 2013 11:22:31 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V6IrQ-0002mR-Fe for linux-arm-kernel@lists.infradead.org; Mon, 05 Aug 2013 11:22:02 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 05 Aug 2013 04:21:09 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 05 Aug 2013 04:20:03 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 05 Aug 2013 04:20:03 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.298.1; Mon, 5 Aug 2013 04:21:40 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH V2 3/8] clk: tegra114: add LP1 suspend/resume support Date: Mon, 5 Aug 2013 19:20:59 +0800 Message-ID: <1375701664-14965-4-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1375701664-14965-1-git-send-email-josephl@nvidia.com> References: <1375701664-14965-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130805_072200_724616_F8186316 X-CRM114-Status: GOOD ( 11.07 ) X-Spam-Score: -1.9 (-) Cc: linux-tegra@vger.kernel.org, Mike Turquette , linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When the system suspends to LP1, the CPU clock source is switched to CLK_M (12MHz Oscillator) during suspend/resume flow. The CPU clock source is controlled by the CCLKG_BURST_POLICY register, and hence this register must be restored during LP1 resume. Cc: Mike Turquette Signed-off-by: Joseph Lo --- V2: * update the commit message --- drivers/clk/tegra/clk-tegra114.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index f74ed19..b0e745a 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "clk.h" @@ -2332,6 +2333,33 @@ void tegra114_clock_deassert_dfll_dvco_reset(void) } EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); +#ifdef CONFIG_PM_SLEEP +static u32 clk_rst_suspend[2]; + +static int tegra114_clk_suspend(void) +{ + u32 *ctx = clk_rst_suspend; + + *ctx++ = readl_relaxed(clk_base + CCLKG_BURST_POLICY); + *ctx++ = readl_relaxed(clk_base + CCLKG_BURST_POLICY + 4); + + return 0; +} + +static void tegra114_clk_resume(void) +{ + u32 *ctx = clk_rst_suspend; + + writel_relaxed(*ctx++, clk_base + CCLKG_BURST_POLICY); + writel_relaxed(*ctx++, clk_base + CCLKG_BURST_POLICY + 4); +} + +static struct syscore_ops tegra114_clk_syscore_ops = { + .suspend = tegra114_clk_suspend, + .resume = tegra114_clk_resume, +}; +#endif + static void __init tegra114_clock_init(struct device_node *np) { struct device_node *node; @@ -2384,5 +2412,9 @@ static void __init tegra114_clock_init(struct device_node *np) tegra_clk_apply_init_table = tegra114_clock_apply_init_table; tegra_cpu_car_ops = &tegra114_cpu_car_ops; + +#ifdef CONFIG_PM_SLEEP + register_syscore_ops(&tegra114_clk_syscore_ops); +#endif } CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);