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Fri, 16 Aug 2013 16:48:18 +0900 (KST) Received: from padma-linuxpc.sisodomain.com ([107.108.83.35]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MRM005Q65O8P080@mmp2.samsung.com>; Fri, 16 Aug 2013 16:48:18 +0900 (KST) From: Padmavathi Venna To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, padma.v@samsung.com, padma.kvr@gmail.com Subject: [PATCH V1 1/4] clk: exynos-audss: add support for Exynos 5420 Date: Fri, 16 Aug 2013 13:19:35 +0530 Message-id: <1376639378-20707-2-git-send-email-padma.v@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1376639378-20707-1-git-send-email-padma.v@samsung.com> References: <1376639378-20707-1-git-send-email-padma.v@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42JZI2JSpet0kzfI4M95BYuV7/8yWkx9+ITN Yv6Rc6wWvQuusllsenyN1WLG+X1MFk8nXGSzaF82h9Xi983vbA6cHrMbLrJ47Jx1l91j06pO No871/aweWxeUu/Rt2UVo8fnTXIB7FFcNimpOZllqUX6dglcGbevX2cpWClRsXv2a6YGxl0i XYycHBICJhJTbn1hgbDFJC7cW8/WxcjFISSwlFHi97I+VpiirVOaoBLTGSW6eg4yQTg9TBIn 7m8GquLgYBPQkWg56wLSICIwmVFid1s+iM0sECtx7/8xJhBbWMBNYlfTVkYQm0VAVeL66n9g cV4BZ4mNLe/ZIZYpSByb+hVsMaeAi8Sste1MIOOFgGpmHhYFWSshsItdYubVVWwQcwQkvk0+ xAJSIyEgK7HpADPEGEmJgytusExgFF7AyLCKUTS1ILmgOCm9yFivODG3uDQvXS85P3cTIzAW Tv971r+D8e4B60OMyUDjJjJLiSbnA2MpryTe0NjMyMLUxNTYyNzSjDRhJXFetRbrQCGB9MSS 1OzU1ILUovii0pzU4kOMTBycUg2M2yaXq6Zf8drH0nvuzhaX8jdR1XyT+80qYlZYWhXyhTOt YlBh51j+vHlbwquAg8bbNPpXPcuf+TP19RyF2QZfjqvbqpl2/mTXu73u7stZPIx7Z55/eVU2 sn53//zve4rjS6QDmTYH1Zbvsb+aujp//V4G0QXZl19/jhMrKPGXXB+6NYFjwQUWJZbijERD Leai4kQAcLmT2psCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKIsWRmVeSWpSXmKPExsVy+t9jQV2nm7xBBrP/iFqsfP+X0WLqwyds FvOPnGO16F1wlc1i0+NrrBYzzu9jsng64SKbRfuyOawWv29+Z3Pg9JjdcJHFY+esu+wem1Z1 snncubaHzWPzknqPvi2rGD0+b5ILYI9qYLTJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1 tLQwV1LIS8xNtVVy8QnQdcvMATpNSaEsMacUKBSQWFyspG+HaUJoiJuuBUxjhK5vSBBcj5EB GkhYw5hx+/p1loKVEhW7Z79mamDcJdLFyMkhIWAisXVKExuELSZx4d56IJuLQ0hgOqNEV89B Jginh0nixP3NrF2MHBxsAjoSLWddQBpEBCYzSuxuywexmQViJe79P8YEYgsLuEnsatrKCGKz CKhKXF/9DyzOK+AssbHlPTvEMgWJY1O/soLYnAIuErPWtjOBjBcCqpl5WHQCI+8CRoZVjKKp BckFxUnpuYZ6xYm5xaV56XrJ+bmbGMGR9kxqB+PKBotDjAIcjEo8vAwTeYOEWBPLiitzDzFK cDArifCuUwEK8aYkVlalFuXHF5XmpBYfYkwGOmois5Rocj4wCeSVxBsam5ibGptamliYmFmS Jqwkznug1TpQSCA9sSQ1OzW1ILUIZgsTB6dUA+NxF5OnsR8MzN/OMVJg36dtEtpUGFptuPDI lotScRnl54u7132QbPc/aLVCTbTA7p1tL3/psnXrJscEaW/ZE2TufZUz445i/6qVd59qfWFp V9D1n7bYIyY26uiDm6dqn51wmcS1v+S8U0hD4/39p799OtpRGuO3WlJTqLf24G+GGTPtji2/ eEGJpTgj0VCLuag4EQAqODh1+AIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130816_034847_193103_30EE43D7 X-CRM114-Status: UNSURE ( 8.46 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -9.7 (---------) Cc: abrestic@chromium.org, kgene.kim@samsung.com, broonie@kernel.org, mturquette@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andrew Bresticker The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by: Andrew Bresticker seviewed-on: https://gerrit.chromium.org/gerrit/57711 Reviewed-by: Simon Glass --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 7 +++++-- drivers/clk/samsung/clk-exynos-audss.c | 8 ++++++++ include/dt-bindings/clk/exynos-audss-clk.h | 3 ++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index a120180..3115930 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -8,8 +8,10 @@ Required Properties: - compatible: should be one of the following: - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. - - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs. - + - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 + SoCs. + - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 + SoCs. - reg: physical base address and length of the controller's register set. - #clock-cells: should be 1. @@ -34,6 +36,7 @@ i2s_bus 6 sclk_i2s 7 pcm_bus 8 sclk_pcm 9 +adma 10 Exynos5420 Example 1: An example of a clock controller node is listed below. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 9b1bbd5..86d2606 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -121,6 +121,12 @@ void __init exynos_audss_clk_init(struct device_node *np) "div_pcm0", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); + if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) { + clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", + "dout_srp", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 9, 0, &lock); + } + #ifdef CONFIG_PM_SLEEP register_syscore_ops(&exynos_audss_clk_syscore_ops); #endif @@ -131,3 +137,5 @@ CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock", exynos_audss_clk_init); CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock", exynos_audss_clk_init); +CLK_OF_DECLARE(exynos5420_audss_clk, "samsung,exynos5420-audss-clock", + exynos_audss_clk_init); diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h index 8279f42..0ae6f5a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -19,7 +19,8 @@ #define EXYNOS_SCLK_I2S 7 #define EXYNOS_PCM_BUS 8 #define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10 -#define EXYNOS_AUDSS_MAX_CLKS 10 +#define EXYNOS_AUDSS_MAX_CLKS 11 #endif