From patchwork Tue Aug 20 02:31:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2846778 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D2178BF546 for ; Tue, 20 Aug 2013 02:35:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F360A202AC for ; Tue, 20 Aug 2013 02:35:19 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DACF3201FB for ; Tue, 20 Aug 2013 02:35:18 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VBbmP-0001yu-2H; Tue, 20 Aug 2013 02:34:45 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VBbm5-0007kJ-AW; Tue, 20 Aug 2013 02:34:25 +0000 Received: from mail-pb0-f47.google.com ([209.85.160.47]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VBblj-0007h2-SV for linux-arm-kernel@lists.infradead.org; Tue, 20 Aug 2013 02:34:05 +0000 Received: by mail-pb0-f47.google.com with SMTP id rr4so5719255pbb.34 for ; Mon, 19 Aug 2013 19:33:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4j4pvgBlmsKhgoUQUYt5BwDm9F9jdZwZTJY6Ggbyw5Q=; b=HWMxbdBuPQ21e3re01Ii1udYpYdetXJoGBU3BrwbgB9P28RQsXa/Ri1GwRXIT6Lm7b 7ZpyVgb35QHIo7GvgRzDOI6IFXbx7MidmK2pkH1L101K+d9zF1Sb7PUcELvdRWkyJcKA a5InoLvs8tGLXEVgTadcF+cogbM+R7guWMjKNpdgIhBg5WhX4HNBf2hXhXGLLsPrkJG0 zCO0XTSgvxaHj6m8p2Q6ECdw2ElWywu8lyf7dLk/x60mN1qbRvxCslGV0/nl3reKdTrT /UYxOQckm1RqMXS4jdUdGZ5phRmLR8uEOkKLuRqstKTppChs0ytHozLRsj0Dh6PFAQmU DI2A== X-Gm-Message-State: ALoCoQluEfUt85QnyeNCF2QeKyPvOwm5zk+J9rayOhsDmzSdoYoOrpe4CRTZRDjYbu9sMxOsA/Cl X-Received: by 10.68.253.161 with SMTP id ab1mr16282032pbd.76.1376966022452; Mon, 19 Aug 2013 19:33:42 -0700 (PDT) Received: from localhost.localdomain ([67.198.247.26]) by mx.google.com with ESMTPSA id xe9sm18067972pbc.21.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 19 Aug 2013 19:33:41 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, john.stultz@linaro.org, mturquette@linaro.org, grant.likely@linar.org, mark.rutland@arm.com Subject: [PATCH v7 03/11] clk: gate: add CLK_GATE_SEPERATED_REG flag Date: Tue, 20 Aug 2013 10:31:05 +0800 Message-Id: <1376965873-14431-4-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1376965873-14431-1-git-send-email-haojian.zhuang@linaro.org> References: <1376965873-14431-1-git-send-email-haojian.zhuang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130819_223404_049501_2AF3C273 X-CRM114-Status: GOOD ( 15.02 ) X-Spam-Score: -2.6 (--) Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In Hisilicon Hi3620 SoC, there're two kinds of clock gates. 1. The same bit in one register controls enabling, disabling or reading status of the clock gate. It's the normal clock gate register. 2. The same bit in three continuous registers control enabling, disabling or reading status of the clock gate. Since these three registers are enabling, disabling and reading status of clock gate. Now reuse common clock gate driver to support the second case with the new CLK_GATE_SEPERATED_REG flag. Signed-off-by: Haojian Zhuang --- drivers/clk/clk-gate.c | 18 +++++++++++++++--- include/linux/clk-provider.h | 7 +++++++ 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 790306e..5dedfb3 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -58,7 +58,10 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) if (set) reg |= BIT(gate->bit_idx); } else { - reg = readl(gate->reg); + if (gate->flags & CLK_GATE_SEPERATED_REG) + reg = 0; + else + reg = readl(gate->reg); if (set) reg |= BIT(gate->bit_idx); @@ -66,7 +69,13 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) reg &= ~BIT(gate->bit_idx); } - writel(reg, gate->reg); + if (gate->flags & CLK_GATE_SEPERATED_REG) { + if (enable) + writel(reg, gate->reg + CLK_GATE_ENABLE_REG); + else + writel(reg, gate->reg + CLK_GATE_DISABLE_REG); + } else + writel(reg, gate->reg); if (gate->lock) spin_unlock_irqrestore(gate->lock, flags); @@ -89,7 +98,10 @@ static int clk_gate_is_enabled(struct clk_hw *hw) u32 reg; struct clk_gate *gate = to_clk_gate(hw); - reg = readl(gate->reg); + if (gate->flags & CLK_GATE_SEPERATED_REG) + reg = readl(gate->reg + CLK_GATE_STATUS_REG); + else + reg = readl(gate->reg); /* if a set bit disables this clk, flip it before masking */ if (gate->flags & CLK_GATE_SET_TO_DISABLE) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 9487b96..0fdc13f 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -214,6 +214,8 @@ void of_fixed_clk_setup(struct device_node *np); * of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. + * CLK_GATE_SEPERATED_REG - The enable, disable & status register are three + * seperated registers. */ struct clk_gate { struct clk_hw hw; @@ -225,6 +227,11 @@ struct clk_gate { #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) +#define CLK_GATE_SEPERATED_REG BIT(2) + +#define CLK_GATE_ENABLE_REG (0x00) +#define CLK_GATE_DISABLE_REG (0x04) +#define CLK_GATE_STATUS_REG (0x08) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name,