From patchwork Thu Aug 22 16:30:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2848336 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5EC869F271 for ; Thu, 22 Aug 2013 16:31:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 83CFB20182 for ; Thu, 22 Aug 2013 16:31:28 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 885672011D for ; Thu, 22 Aug 2013 16:31:23 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCXmx-0003kS-3l; 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envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail50-ch1 (localhost.localdomain [127.0.0.1]) by mail50-ch1 (MessageSwitch) id 1377189020770731_6310; Thu, 22 Aug 2013 16:30:20 +0000 (UTC) Received: from CH1EHSMHS011.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.242]) by mail50-ch1.bigfish.com (Postfix) with ESMTP id B4A5D1C004A; Thu, 22 Aug 2013 16:30:20 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by CH1EHSMHS011.bigfish.com (10.43.70.11) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 22 Aug 2013 16:30:20 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Thu, 22 Aug 2013 09:19:30 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.121]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r7MGUG6e001772; Thu, 22 Aug 2013 09:30:19 -0700 (PDT) From: To: Subject: [PATCHv4 2/4] arm: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timer Date: Thu, 22 Aug 2013 11:30:24 -0500 Message-ID: <1377189026-16656-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377189026-16656-1-git-send-email-dinguyen@altera.com> References: <1377189026-16656-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130822_123044_534457_A95FC1F9 X-CRM114-Status: GOOD ( 12.94 ) X-Spam-Score: -2.6 (--) Cc: Mark Rutland , devicetree@vger.kernel.org, John Stultz , Ian Campbell , Pawel Moll , Stephen Warren , Pavel Machek , Rob Herring , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Olof Johansson , Jamie Iles , Dinh Nguyen , Heiko Stuebner X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen "dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the DW APB timer, just fed by different clocks. Thus, deprecate both "dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer". Signed-off-by: Dinh Nguyen Reviewed-by: Pavel Machek CC: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell CC: Arnd Bergmann Cc: Olof Johansson CC: Jamie Iles Cc: John Stultz Cc: Heiko Stuebner Cc: Pavel Machek Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org v3: - Split out a separate that cleans up the timer entries and clock information. - Clearly states which binding is deprecated in the bindingd doc. v2: - Deprecate the "dw-apb-timer-osc" and "dw-apb-timer-sp" but maintain backwards compatibility in the driver. Acked-by: Stephen Warren --- Documentation/devicetree/bindings/rtc/dw-apb.txt | 34 +++++++--------------- arch/arm/boot/dts/socfpga.dtsi | 8 ++--- 2 files changed, 15 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt index eb2327b..c703d51 100644 --- a/Documentation/devicetree/bindings/rtc/dw-apb.txt +++ b/Documentation/devicetree/bindings/rtc/dw-apb.txt @@ -1,7 +1,10 @@ * Designware APB timer Required properties: -- compatible: "snps,dw-apb-timer-sp" or "snps,dw-apb-timer-osc" +- compatible: One of: + "snps,dw-apb-timer" + "snps,dw-apb-timer-sp" + "snps,dw-apb-timer-osc" - reg: physical base address of the controller and length of memory mapped region. - interrupts: IRQ line for the timer. @@ -20,25 +23,10 @@ systems may use one. Example: - - timer1: timer@ffc09000 { - compatible = "snps,dw-apb-timer-sp"; - interrupts = <0 168 4>; - clock-frequency = <200000000>; - reg = <0xffc09000 0x1000>; - }; - - timer2: timer@ffd00000 { - compatible = "snps,dw-apb-timer-osc"; - interrupts = <0 169 4>; - clock-frequency = <200000000>; - reg = <0xffd00000 0x1000>; - }; - - timer3: timer@ffe00000 { - compatible = "snps,dw-apb-timer-osc"; - interrupts = <0 170 4>; - reg = <0xffe00000 0x1000>; - clocks = <&timer_clk>, <&timer_pclk>; - clock-names = "timer", "pclk"; - }; + timer@ffe00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clocks = <&timer_clk>, <&timer_pclk>; + clock-names = "timer", "pclk"; + }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2cb5cb7..d9fda91 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -472,28 +472,28 @@ }; timer@ffc08000 { - compatible = "snps,dw-apb-timer-sp"; + compatible = "snps,dw-apb-timer"; interrupts = <0 167 4>; reg = <0xffc08000 0x1000>; clocks = <&osc>; }; timer@ffc09000 { - compatible = "snps,dw-apb-timer-sp"; + compatible = "snps,dw-apb-timer"; interrupts = <0 168 4>; reg = <0xffc09000 0x1000>; clocks = <&osc>; }; timer@ffd00000 { - compatible = "snps,dw-apb-timer-osc"; + compatible = "snps,dw-apb-timer"; interrupts = <0 169 4>; reg = <0xffd00000 0x1000>; clocks = <&l4_sp_clk>; }; timer@ffd01000 { - compatible = "snps,dw-apb-timer-osc"; + compatible = "snps,dw-apb-timer"; interrupts = <0 170 4>; reg = <0xffd01000 0x1000>; clocks = <&l4_sp_clk>;