| Message ID | 1377241078-11808-6-git-send-email-rahul.sharma@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Rahul, On Friday 23 of August 2013 12:27:58 Rahul Sharma wrote: > sclk_pixel is used to represent pixel clock divider on all exynos > SoCs not as a gate clock. It is queried in driver to pass as the > parent to hdmi clock while switching between parents. A new ID can > be asssigned Pixel gate clock which is currently not in use. Pixel > clock gate is default 'on'. This doesn't sound like a correct assumption, especially if you recall how common clock framework works - it disables any unclaimed clock automatically. Also we might want to support gating from power management reasons. IMHO you should simply export the dout_hdmi_pixel clock, keeping the original sclk_pixel exported as well. Best regards, Tomasz
On 24 August 2013 01:32, Tomasz Figa <tomasz.figa@gmail.com> wrote: > Hi Rahul, > > On Friday 23 of August 2013 12:27:58 Rahul Sharma wrote: >> sclk_pixel is used to represent pixel clock divider on all exynos >> SoCs not as a gate clock. It is queried in driver to pass as the >> parent to hdmi clock while switching between parents. A new ID can >> be asssigned Pixel gate clock which is currently not in use. Pixel >> clock gate is default 'on'. > > This doesn't sound like a correct assumption, especially if you recall how > common clock framework works - it disables any unclaimed clock > automatically. Also we might want to support gating from power management > reasons. > > IMHO you should simply export the dout_hdmi_pixel clock, keeping the > original sclk_pixel exported as well. > Hi Tomasz, Yea correct. I will export the divider clock and let hdmi driver use that to pass as parent opf mout_pixel. Regards, Rahul Sharma. > Best regards, > Tomasz >
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 5f9bc63..8eb3c42 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -463,7 +463,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), - DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), + DIV(sclk_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), /* Audio Block */ DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), @@ -599,7 +599,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), - GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", + GATE(none, "sclk_pixel", "dout_hdmi_pixel", GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), GATE(sclk_dp1, "sclk_dp1", "dout_dp1", GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
sclk_pixel is used to represent pixel clock divider on all exynos SoCs not as a gate clock. It is queried in driver to pass as the parent to hdmi clock while switching between parents. A new ID can be asssigned Pixel gate clock which is currently not in use. Pixel clock gate is default 'on'. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> --- drivers/clk/samsung/clk-exynos5420.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)