From patchwork Fri Aug 23 07:21:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 2848583 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C3D4FBF546 for ; Fri, 23 Aug 2013 07:22:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A98F8202AC for ; Fri, 23 Aug 2013 07:22:14 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 284342021C for ; Fri, 23 Aug 2013 07:22:10 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VClh6-00050r-PQ; Fri, 23 Aug 2013 07:22:05 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VClh4-0002xi-JV; Fri, 23 Aug 2013 07:22:02 +0000 Received: from mail-pd0-f175.google.com ([209.85.192.175]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VClgy-0002xH-7s for linux-arm-kernel@lists.infradead.org; Fri, 23 Aug 2013 07:22:00 +0000 Received: by mail-pd0-f175.google.com with SMTP id q10so335436pdj.34 for ; Fri, 23 Aug 2013 00:21:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=JKBM5ZPYViRGvU+AXeboY65TyhczwiO8PQMe5t5au04=; b=SVj3OvgxmMhZwx5/13+pg7rvyj59sWyMQ6dksTDN5M8001Hs2ovX30ul9UwJQiRZA9 aFteDW5/G1FbFJMxFxm+ce1OIRA06WJfDXX+ElvUk4STIZWkuYCFKkn/rxjUl/MFYOxd WKt6CzkU20kF8mr3u36V/Gap3C+7VoXYesZVEQVhxXAQ3tSTYKN+ZOukPXO2CqFqF+Co BshAqaoP2PKy4TZGIjMbkDyfhBwaxPd9a+JLv5CESNNZEZuY8NuVNSxoeHeI9ySg5o6K W6VtABeVAvbqLUoQimP6BxSPCk2mltH1QdvLG89Md+DnjcgVrg2ilcaG+EzYcvjKgrG1 3LpQ== X-Gm-Message-State: ALoCoQkXMmXcBZquFeIsg5rK53vPGnKA3BgskE/x79PfCpIlWQw5FFVAN2BqVb+ZL6DNQKQXEMD+ X-Received: by 10.66.162.136 with SMTP id ya8mr9516191pab.110.1377242494147; Fri, 23 Aug 2013 00:21:34 -0700 (PDT) Received: from localhost.localdomain (c-67-169-183-77.hsd1.ca.comcast.net. [67.169.183.77]) by mx.google.com with ESMTPSA id oj6sm21574581pab.9.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 23 Aug 2013 00:21:33 -0700 (PDT) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu Subject: [RFC PATCH] ARM: KVM: vgic: Bump VGIC_NR_IRQS to 256 Date: Fri, 23 Aug 2013 00:21:30 -0700 Message-Id: <1377242490-30132-1-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130823_032156_371980_C5C4725F X-CRM114-Status: GOOD ( 13.24 ) X-Spam-Score: 0.6 (/) Cc: Christoffer Dall , linaro-kernel@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, SUSPICIOUS_RECIPS, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Versatile Express TC2 board, which we use as our main emulated platform in QEMU, defines 160+32 == 192 interrupts, so limiting the number of interrupts to 128 is not quite going to cut it for real board emulation. Note that this didn't use to be a problem because QEMU was buggy and only defined 128 interrupts until recently. [ Sending this as an RFC, because I haven't convinced myself that this is even the right short-term fix. On a longer-term we probably need a way for QEMU to tell the kernel how many IRQs it needs for a particular implementation of a CPU and a GIC, but on a shorter term we should at least support a real A15 configuration. Note that this change increases the in-kernel memory consumption quite a bit, especially due to the irq-to-lr map, which could be reversed or turned into a hash table or list, at the sacrifice of some performance during world-switches to search the data structure. ] Signed-off-by: Christoffer Dall --- include/kvm/arm_vgic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 343744e..7e2d158 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -26,7 +26,7 @@ #include #include -#define VGIC_NR_IRQS 128 +#define VGIC_NR_IRQS 256 #define VGIC_NR_SGIS 16 #define VGIC_NR_PPIS 16 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)