From patchwork Fri Aug 23 15:44:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2848882 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AD6549F2F4 for ; Fri, 23 Aug 2013 15:45:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D813220171 for ; Fri, 23 Aug 2013 15:45:21 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 77BB82014A for ; Fri, 23 Aug 2013 15:45:20 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCtXv-000588-W7; Fri, 23 Aug 2013 15:45:08 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCtXt-0006qt-Lx; Fri, 23 Aug 2013 15:45:05 +0000 Received: from ch1ehsobe001.messaging.microsoft.com ([216.32.181.181] helo=ch1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCtXr-0006pn-0m for linux-arm-kernel@lists.infradead.org; Fri, 23 Aug 2013 15:45:04 +0000 Received: from mail187-ch1-R.bigfish.com (10.43.68.244) by CH1EHSOBE019.bigfish.com (10.43.70.76) with Microsoft SMTP Server id 14.1.225.22; Fri, 23 Aug 2013 15:44:41 +0000 Received: from mail187-ch1 (localhost [127.0.0.1]) by mail187-ch1-R.bigfish.com (Postfix) with ESMTP id 863B63E0281; Fri, 23 Aug 2013 15:44:41 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh8275dh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h1155h) Received-SPF: pass (mail187-ch1: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail187-ch1 (localhost.localdomain [127.0.0.1]) by mail187-ch1 (MessageSwitch) id 1377272680483196_3570; Fri, 23 Aug 2013 15:44:40 +0000 (UTC) Received: from CH1EHSMHS024.bigfish.com (snatpool3.int.messaging.microsoft.com [10.43.68.228]) by mail187-ch1.bigfish.com (Postfix) with ESMTP id 7021118004C; Fri, 23 Aug 2013 15:44:40 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by CH1EHSMHS024.bigfish.com (10.43.70.24) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 23 Aug 2013 15:44:39 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Fri, 23 Aug 2013 08:33:48 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.121]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r7NFiZ6f008050; Fri, 23 Aug 2013 08:44:38 -0700 (PDT) From: To: Subject: [PATCHv5 3/3] mmc: dw_mmc: Use phandle to get SDR timing values from sys-mgr Date: Fri, 23 Aug 2013 10:44:46 -0500 Message-ID: <1377272686-13253-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377272686-13253-1-git-send-email-dinguyen@altera.com> References: <1377272686-13253-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130823_114503_243356_6785735D X-CRM114-Status: GOOD ( 14.78 ) X-Spam-Score: -2.6 (--) Cc: Mark Rutland , devicetree@vger.kernel.org, Ian Campbell , Pawel Moll , Stephen Warren , Seungwon Jeon , linux-mmc@vger.kernel.org, Rob Herring , Jaehoon Chung , linux-arm-kernel@lists.infradead.org, Chris Ball , Dinh Nguyen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen Update the driver to get the system manager node from a phandle. Also, the driver can get the correct clock value from the common clock API, thus the "altr,dw-mshc-ciu-div" binding is not needed at all. Signed-off-by: Dinh Nguyen Cc: Jaehoon Chung Cc: Seungwon Jeon Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell Cc: Chris Ball Cc: devicetree@vger.kernel.org Cc: linux-mmc@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org v2: - Use "altr,ciu-clk-offset" to get the correct CIU clock values to be set in the system manager. --- drivers/mmc/host/dw_mmc-socfpga.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c index 14b5961..cfd67e1 100644 --- a/drivers/mmc/host/dw_mmc-socfpga.c +++ b/drivers/mmc/host/dw_mmc-socfpga.c @@ -24,21 +24,20 @@ #include "dw_mmc.h" #include "dw_mmc-pltfm.h" -#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 -#define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7 -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) +#define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7 /* SOCFPGA implementation specific driver private data */ struct dw_mci_socfpga_priv_data { - u8 ciu_div; /* card interface unit divisor */ u32 hs_timing; /* bitmask for CIU clock phase shift */ struct regmap *sysreg; /* regmap for system manager register */ + /* Offset for the ciu clock setting register inside the system manager.*/ + u32 ciu_clk_offset; }; static int dw_mci_socfpga_priv_init(struct dw_mci *host) { struct dw_mci_socfpga_priv_data *priv; + struct device_node *np = host->dev->of_node; priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); if (!priv) { @@ -46,9 +45,9 @@ static int dw_mci_socfpga_priv_init(struct dw_mci *host) return -ENOMEM; } - priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); + priv->sysreg = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr"); if (IS_ERR(priv->sysreg)) { - dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n"); + dev_err(host->dev, "No sysmgr phandle specified!\n"); return PTR_ERR(priv->sysreg); } host->priv = priv; @@ -61,11 +60,8 @@ static int dw_mci_socfpga_setup_clock(struct dw_mci *host) struct dw_mci_socfpga_priv_data *priv = host->priv; clk_disable_unprepare(host->ciu_clk); - regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, - priv->hs_timing); + regmap_write(priv->sysreg, priv->ciu_clk_offset, priv->hs_timing); clk_prepare_enable(host->ciu_clk); - - host->bus_hz /= (priv->ciu_div + 1); return 0; } @@ -82,20 +78,21 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host) struct dw_mci_socfpga_priv_data *priv = host->priv; struct device_node *np = host->dev->of_node; u32 timing[2]; - u32 div = 0; + u32 offset[3]; int ret; - ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div); - if (ret) - dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1"); - priv->ciu_div = div; - ret = of_property_read_u32_array(np, "altr,dw-mshc-sdr-timing", timing, 2); if (ret) return ret; - priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); + ret = of_property_read_u32_array(np, "altr,ciu-clk-offset", offset, 3); + if (ret) + return ret; + + priv->ciu_clk_offset = offset[0]; + priv->hs_timing = + ((((timing[0]) & 0x7) << offset[2]) | (((timing[1]) & 0x7) << offset[1])); return 0; }