From patchwork Fri Aug 23 19:32:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 2849024 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5E7509F239 for ; Fri, 23 Aug 2013 19:34:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6B5E6203C4 for ; Fri, 23 Aug 2013 19:34:13 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 31CB420279 for ; Fri, 23 Aug 2013 19:34:12 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCx77-0003QT-F4; Fri, 23 Aug 2013 19:33:41 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCx6s-0004Wt-9Q; Fri, 23 Aug 2013 19:33:26 +0000 Received: from svenfoo.org ([82.94.215.22] helo=mail.zonque.de) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCx67-0004RK-1A for linux-arm-kernel@lists.infradead.org; Fri, 23 Aug 2013 19:32:44 +0000 Received: from localhost (localhost [127.0.0.1]) by mail.zonque.de (Postfix) with ESMTP id E2A31C1683; Fri, 23 Aug 2013 21:32:18 +0200 (CEST) Received: from mail.zonque.de ([127.0.0.1]) by localhost (rambrand.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PkSfVYtQ-C_b; Fri, 23 Aug 2013 21:32:18 +0200 (CEST) Received: from tamtam.fritz.box (p5DDC680F.dip0.t-ipconnect.de [93.220.104.15]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.zonque.de (Postfix) with ESMTPSA id 2752FC1601; Fri, 23 Aug 2013 21:32:18 +0200 (CEST) From: Daniel Mack To: netdev@vger.kernel.org Subject: [PATCH v6 4/5] net: ethernet: cpsw: add support for hardware interface mode config Date: Fri, 23 Aug 2013 21:32:09 +0200 Message-Id: <1377286330-29663-5-git-send-email-zonque@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1377286330-29663-1-git-send-email-zonque@gmail.com> References: <1377286330-29663-1-git-send-email-zonque@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130823_153239_470580_5B6D0680 X-CRM114-Status: GOOD ( 18.69 ) X-Spam-Score: -0.3 (/) Cc: mugunthanvnm@ti.com, sergei.shtylyov@cogentembedded.com, d-gerlach@ti.com, nsekhar@ti.com, vaibhav.bedia@ti.com, Daniel Mack , devicetree@vger.kernel.org, bcousson@baylibre.com, ujhelyi.m@gmail.com, linux-omap@vger.kernel.org, davem@davemloft.net, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FREEMAIL_FROM,RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The cpsw currently lacks code to properly set up the hardware interface mode on AM33xx. Other platforms might be equally affected. Usually, the bootloader will configure the control module register, so probably that's why such support wasn't needed in the past. In suspend mode though, this register is modified, and so it needs reprogramming after resume. This patch adds code that makes use of the previously added and optional support for passing the control mode register, and configures the correct register bits when the slave is opened. The AM33xx also has a bit for each slave to configure the RMII reference clock direction. Setting it is now supported by a per-slave DT property. This code path introducted by this patch is currently exclusive for am33xx. Signed-off-by: Daniel Mack Acked-by: Mugunthan V N --- Documentation/devicetree/bindings/net/cpsw.txt | 2 + drivers/net/ethernet/ti/cpsw.c | 58 ++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw.h | 8 ++++ 3 files changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index b717458..0895a51 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt @@ -34,6 +34,8 @@ Required properties: - phy_id : Specifies slave phy id - phy-mode : The interface between the SoC and the PHY (a string that of_get_phy_mode() can understand) +- ti,rmii-clock-ext : If present, the driver will configure the RMII + interface to external clock usage - mac-address : Specifies slave MAC address Optional properties: diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 8d023ab..6b47e78 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -980,6 +980,60 @@ static inline void cpsw_add_dual_emac_def_ale_entries( priv->host_port, ALE_VLAN, slave->port_vlan); } +static void cpsw_set_phy_interface_mode(struct cpsw_slave *slave, + struct cpsw_priv *priv) +{ + u32 reg; + u32 mask; + u32 mode = 0; + + switch (priv->data.hw_type) { + case CPSW_TYPE_AM33XX: + if (IS_ERR_OR_NULL(priv->gmii_sel_reg)) + break; + + reg = readl(priv->gmii_sel_reg); + + if (slave->phy) { + switch (slave->phy->interface) { + case PHY_INTERFACE_MODE_MII: + default: + mode = AM33XX_GMII_SEL_MODE_MII; + break; + case PHY_INTERFACE_MODE_RMII: + mode = AM33XX_GMII_SEL_MODE_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + mode = AM33XX_GMII_SEL_MODE_RGMII; + break; + }; + } + + mask = 0x3 << (slave->slave_num * 2) | + BIT(slave->slave_num + 6); + mode <<= slave->slave_num * 2; + + if (slave->data->rmii_clock_external) { + if (slave->slave_num == 0) + mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN; + else + mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN; + } + + reg &= ~mask; + reg |= mode; + + writel(reg, priv->gmii_sel_reg); + break; + + default: + break; + } +} + static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) { char name[32]; @@ -1028,6 +1082,8 @@ static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) slave->phy->phy_id); phy_start(slave->phy); } + + cpsw_set_phy_interface_mode(slave, priv); } static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) @@ -1823,6 +1879,8 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data, memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); slave_data->phy_if = of_get_phy_mode(slave_node); + if (of_find_property(slave_node, "ti,rmii-clock-ext", NULL)) + slave_data->rmii_clock_external = true; if (data->dual_emac) { if (of_property_read_u32(slave_node, "dual_emac_res_vlan", diff --git a/drivers/net/ethernet/ti/cpsw.h b/drivers/net/ethernet/ti/cpsw.h index 96c374a..3a6cb16 100644 --- a/drivers/net/ethernet/ti/cpsw.h +++ b/drivers/net/ethernet/ti/cpsw.h @@ -19,6 +19,7 @@ struct cpsw_slave_data { char phy_id[MII_BUS_ID_SIZE]; int phy_if; + bool rmii_clock_external; u8 mac_addr[ETH_ALEN]; u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */ }; @@ -40,4 +41,11 @@ struct cpsw_platform_data { u32 hw_type; /* hardware type as specified in 'compatible' */ }; +/* SoC specific definitions for the CONTROL port */ +#define AM33XX_GMII_SEL_MODE_MII 0 +#define AM33XX_GMII_SEL_MODE_RMII 1 +#define AM33XX_GMII_SEL_MODE_RGMII 2 + +#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7) +#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6) #endif /* __CPSW_H__ */