From patchwork Mon Aug 26 05:39:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chaiken, Alison" X-Patchwork-Id: 2849392 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0AF60BF546 for ; Mon, 26 Aug 2013 05:40:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4D2D420115 for ; Mon, 26 Aug 2013 05:40:21 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3958E200F1 for ; Mon, 26 Aug 2013 05:40:19 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VDpXD-0004by-7d; Mon, 26 Aug 2013 05:40:15 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VDpXB-0005Ms-3s; Mon, 26 Aug 2013 05:40:13 +0000 Received: from relay1.mentorg.com ([192.94.38.131]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VDpX5-0005MR-Vt for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2013 05:40:11 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1VDpWZ-0002du-2n from Alison_Chaiken@mentor.com ; Sun, 25 Aug 2013 22:39:35 -0700 Received: from NA1-MAIL.mgc.mentorg.com ([147.34.98.181]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Sun, 25 Aug 2013 22:39:35 -0700 Received: from she-devel.mgc.mentorg.com ([172.30.5.27]) by NA1-MAIL.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 25 Aug 2013 22:39:34 -0700 From: alison_chaiken@mentor.com To: linus.walleij@linaro.org Subject: [PATCH] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 0 IMX6DQRM Date: Sun, 25 Aug 2013 22:39:28 -0700 Message-Id: <1377495568-9368-1-git-send-email-alison_chaiken@mentor.com> X-Mailer: git-send-email 1.7.10.4 X-OriginalArrivalTime: 26 Aug 2013 05:39:34.0420 (UTC) FILETIME=[A52C8540:01CEA21E] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130826_014009_710479_EF5DE788 X-CRM114-Status: UNSURE ( 4.86 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) Cc: devicetree@vger.kernel.org, alison@she-devel.com, rob.herring@calxeda.com, b32955@freescale.com, olof@lixom.net, alison_chaiken@mentor.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Alison Chaiken Update imx6.dtsi iomuxc pinctrl config settings to reflect Table 4-1 of Rev. 0 (11/2012) of IMX6DQRM, i.MX6 technical reference manual. Impact: USDHC: increase drive speed and impedance. I2C and EIM: change drive impedance and disable open-drain. ECSPI: change drive impedance. ESAI and ENET: probably pedantic changes. Signed-off-by: Alison Chaiken --- arch/arm/boot/dts/imx6dl.dtsi | 148 +++++++++++++-------------- arch/arm/boot/dts/imx6q.dtsi | 226 ++++++++++++++++++++--------------------- arch/arm/boot/dts/imx6sl.dtsi | 48 ++++----- 3 files changed, 211 insertions(+), 211 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 2b3ecd6..36075b0 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -51,9 +51,9 @@ ecspi1 { pinctrl_ecspi1_1: ecspi1grp-1 { fsl,pins = < - MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x1b0b0 + MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x1b0b0 + MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x1b0b0 >; }; }; @@ -63,19 +63,19 @@ fsl,pins = < MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x13030 + MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x13030 + MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 >; }; @@ -84,19 +84,19 @@ fsl,pins = < MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x13030 + MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x13030 + MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 >; }; }; @@ -104,23 +104,23 @@ gpmi-nand { pinctrl_gpmi_nand_1: gpmi-nand-1 { fsl,pins = < - MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + MX6DL_PAD_NANDF_CLE__NAND_CLE 0x1b0b0 + MX6DL_PAD_NANDF_ALE__NAND_ALE 0x1b0b0 + MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x1b0b0 + MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x1b0b0 + MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x1b0b0 + MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x1b0b0 + MX6DL_PAD_SD4_CMD__NAND_RE_B 0x1b0b0 + MX6DL_PAD_SD4_CLK__NAND_WE_B 0x1b0b0 + MX6DL_PAD_NANDF_D0__NAND_DATA00 0x1b0b0 + MX6DL_PAD_NANDF_D1__NAND_DATA01 0x1b0b0 + MX6DL_PAD_NANDF_D2__NAND_DATA02 0x1b0b0 + MX6DL_PAD_NANDF_D3__NAND_DATA03 0x1b0b0 + MX6DL_PAD_NANDF_D4__NAND_DATA04 0x1b0b0 + MX6DL_PAD_NANDF_D5__NAND_DATA05 0x1b0b0 + MX6DL_PAD_NANDF_D6__NAND_DATA06 0x1b0b0 + MX6DL_PAD_NANDF_D7__NAND_DATA07 0x1b0b0 + MX6DL_PAD_SD4_DAT0__NAND_DQS 0x1b0b0 >; }; }; @@ -128,8 +128,8 @@ i2c1 { pinctrl_i2c1_2: i2c1grp-2 { fsl,pins = < - MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b0b0 + MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b0b0 >; }; }; @@ -137,8 +137,8 @@ uart1 { pinctrl_uart1_1: uart1grp-1 { fsl,pins = < - MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0 + MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0 >; }; }; @@ -146,8 +146,8 @@ uart4 { pinctrl_uart4_1: uart4grp-1 { fsl,pins = < - MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b0 + MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b0 >; }; }; @@ -155,7 +155,7 @@ usbotg { pinctrl_usbotg_2: usbotggrp-2 { fsl,pins = < - MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 >; }; }; @@ -163,16 +163,16 @@ usdhc2 { pinctrl_usdhc2_1: usdhc2grp-1 { fsl,pins = < - MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6DL_PAD_SD2_CMD__SD2_CMD 0x1b0b0 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059 + MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0 + MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0 + MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0 + MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0 + MX6DL_PAD_NANDF_D4__SD2_DATA4 0x1b0b0 + MX6DL_PAD_NANDF_D5__SD2_DATA5 0x1b0b0 + MX6DL_PAD_NANDF_D6__SD2_DATA6 0x1b0b0 + MX6DL_PAD_NANDF_D7__SD2_DATA7 0x1b0b0 >; }; }; @@ -180,27 +180,27 @@ usdhc3 { pinctrl_usdhc3_1: usdhc3grp-1 { fsl,pins = < - MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6DL_PAD_SD3_CMD__SD3_CMD 0x1b0b0 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0 + MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0 + MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0 + MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0 + MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x1b0b0 + MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x1b0b0 + MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x1b0b0 + MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x1b0b0 >; }; pinctrl_usdhc3_2: usdhc3grp_2 { fsl,pins = < - MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6DL_PAD_SD3_CMD__SD3_CMD 0x1b0b0 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0 + MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0 + MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0 + MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0 >; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index ba09dc3..826bfe0 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -103,9 +103,9 @@ ecspi1 { pinctrl_ecspi1_1: ecspi1grp-1 { fsl,pins = < - MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x1b0b0 + MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x1b0b0 + MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x1b0b0 >; }; }; @@ -125,19 +125,19 @@ fsl,pins = < MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x13030 + MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x13030 + MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 >; }; @@ -146,19 +146,19 @@ fsl,pins = < MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x13030 + MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x13030 + MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 >; }; @@ -166,19 +166,19 @@ fsl,pins = < MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x13030 + MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x13030 + MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 >; }; @@ -187,22 +187,22 @@ gpmi-nand { pinctrl_gpmi_nand_1: gpmi-nand-1 { fsl,pins = < - MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6Q_PAD_NANDF_CLE__NAND_CLE 0x1b0b0 + MX6Q_PAD_NANDF_ALE__NAND_ALE 0x1b0b0 + MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x1b0b0 + MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x1b0b0 + MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x1b0b0 + MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x1b0b0 + MX6Q_PAD_SD4_CMD__NAND_RE_B 0x1b0b0 + MX6Q_PAD_SD4_CLK__NAND_WE_B 0x1b0b0 + MX6Q_PAD_NANDF_D0__NAND_DATA00 0x1b0b0 + MX6Q_PAD_NANDF_D1__NAND_DATA01 0x1b0b0 + MX6Q_PAD_NANDF_D2__NAND_DATA02 0x1b0b0 + MX6Q_PAD_NANDF_D3__NAND_DATA03 0x1b0b0 + MX6Q_PAD_NANDF_D4__NAND_DATA04 0x1b0b0 + MX6Q_PAD_NANDF_D5__NAND_DATA05 0x1b0b0 + MX6Q_PAD_NANDF_D6__NAND_DATA06 0x1b0b0 + MX6Q_PAD_NANDF_D7__NAND_DATA07 0x1b0b0 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1 >; }; @@ -211,15 +211,15 @@ i2c1 { pinctrl_i2c1_1: i2c1grp-1 { fsl,pins = < - MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b0b0 + MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b0b0 >; }; pinctrl_i2c1_2: i2c1grp-2 { fsl,pins = < - MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b0b0 + MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b0b0 >; }; }; @@ -227,8 +227,8 @@ i2c2 { pinctrl_i2c2_1: i2c2grp-1 { fsl,pins = < - MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b0b0 + MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b0b0 >; }; }; @@ -236,8 +236,8 @@ i2c3 { pinctrl_i2c3_1: i2c3grp-1 { fsl,pins = < - MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b0b0 + MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b0b0 >; }; }; @@ -245,8 +245,8 @@ uart1 { pinctrl_uart1_1: uart1grp-1 { fsl,pins = < - MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0 + MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0 >; }; }; @@ -254,8 +254,8 @@ uart2 { pinctrl_uart2_1: uart2grp-1 { fsl,pins = < - MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b0 + MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b0 >; }; }; @@ -263,8 +263,8 @@ uart4 { pinctrl_uart4_1: uart4grp-1 { fsl,pins = < - MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b0 + MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b0 >; }; }; @@ -272,13 +272,13 @@ usbotg { pinctrl_usbotg_1: usbotggrp-1 { fsl,pins = < - MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6Q_PAD_GPIO_1__USB_OTG_ID 0x1b0b0 >; }; pinctrl_usbotg_2: usbotggrp-2 { fsl,pins = < - MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 >; }; }; @@ -286,27 +286,27 @@ usdhc2 { pinctrl_usdhc2_1: usdhc2grp-1 { fsl,pins = < - MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6Q_PAD_SD2_CMD__SD2_CMD 0x1b0b0 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 + MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0 + MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0 + MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0 + MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0 + MX6Q_PAD_NANDF_D4__SD2_DATA4 0x1b0b0 + MX6Q_PAD_NANDF_D5__SD2_DATA5 0x1b0b0 + MX6Q_PAD_NANDF_D6__SD2_DATA6 0x1b0b0 + MX6Q_PAD_NANDF_D7__SD2_DATA7 0x1b0b0 >; }; pinctrl_usdhc2_2: usdhc2grp-2 { fsl,pins = < - MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6Q_PAD_SD2_CMD__SD2_CMD 0x1b0b0 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0 + MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0 + MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0 + MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0 >; }; }; @@ -314,27 +314,27 @@ usdhc3 { pinctrl_usdhc3_1: usdhc3grp-1 { fsl,pins = < - MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6Q_PAD_SD3_CMD__SD3_CMD 0x1b0b0 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0 + MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0 + MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0 + MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0 + MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x1b0b0 + MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x1b0b0 + MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x1b0b0 + MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x1b0b0 >; }; pinctrl_usdhc3_2: usdhc3grp-2 { fsl,pins = < - MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6Q_PAD_SD3_CMD__SD3_CMD 0x1b0b0 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0 + MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0 + MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0 + MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0 >; }; }; @@ -342,27 +342,27 @@ usdhc4 { pinctrl_usdhc4_1: usdhc4grp-1 { fsl,pins = < - MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6Q_PAD_SD4_CMD__SD4_CMD 0x1b0b0 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059 + MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x1b0b0 + MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x1b0b0 + MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x1b0b0 + MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x1b0b0 + MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x1b0b0 + MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x1b0b0 + MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x1b0b0 + MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x1b0b0 >; }; pinctrl_usdhc4_2: usdhc4grp-2 { fsl,pins = < - MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6Q_PAD_SD4_CMD__SD4_CMD 0x1b0b0 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x1b0b0 + MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x1b0b0 + MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x1b0b0 + MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x1b0b0 >; }; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c5e5da0..81edb19 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -527,8 +527,8 @@ uart1 { pinctrl_uart1_1: uart1grp-1 { fsl,pins = < - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b0 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b0 >; }; }; @@ -536,16 +536,16 @@ usdhc1 { pinctrl_usdhc1_1: usdhc1grp-1 { fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 + MX6SL_PAD_SD1_CMD__SD1_CMD 0x1b0b0 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x1b0b0 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x1b0b0 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x1b0b0 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x1b0b0 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x1b0b0 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x1b0b0 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x1b0b0 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x1b0b0 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x1b0b0 >; }; }; @@ -553,12 +553,12 @@ usdhc2 { pinctrl_usdhc2_1: usdhc2grp-1 { fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6SL_PAD_SD2_CMD__SD2_CMD 0x1b0b0 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x1b0b0 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0 >; }; }; @@ -566,12 +566,12 @@ usdhc3 { pinctrl_usdhc3_1: usdhc3grp-1 { fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6SL_PAD_SD3_CMD__SD3_CMD 0x1b0b0 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x1b0b0 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0 >; }; };