From patchwork Mon Aug 26 15:36:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 2849665 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7EB539F271 for ; Mon, 26 Aug 2013 15:38:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 518FA2037E for ; Mon, 26 Aug 2013 15:38:56 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A22320386 for ; Mon, 26 Aug 2013 15:38:55 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VDyrp-0006nP-CI; Mon, 26 Aug 2013 15:38:09 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VDyrV-0002bF-H4; Mon, 26 Aug 2013 15:37:49 +0000 Received: from mail-ee0-f54.google.com ([74.125.83.54]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VDyqs-0002Y5-Md for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2013 15:37:11 +0000 Received: by mail-ee0-f54.google.com with SMTP id e53so1718847eek.27 for ; Mon, 26 Aug 2013 08:36:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nigvde4RDhJQcZ9Q8y0joZYPc94sN+KbfjGGnHVW9G8=; b=azhvydm803x6cTtLUsm6DOVZtpvPOY41EJEE+DJ76WVPhsIrmZJNrRhyokN0niNu1Q om1wJ9xMPSykVy031asA6xm/m+YjzVT5djKe1msQx+bd4d+EM4XiqvUH654Mwv5FxQnW shGM1m18NCbbbVrTAE44U0BxCB0bPsYwJX3Kr2waBhmm6DU0jscbJNiVCLfew1VjrBhs 3yWHZU0vJKOn/DvXr+rx6fsPhyByQfmWAhBZ1fCenNohTMaWS2q/uTabtlzKoj5Tgs2F fJJ2P8ek95p8viy6hZXz3Ezg483PEE2ohhZWqT9bDXs4VNbjnwTtDVcZuh2J7l5v8x/B i3dA== X-Gm-Message-State: ALoCoQkZLXddsEGLlW7DkGK7hTpv4R4xIG0U2ct++IsXb+5l8tUTw5YupjMvJKhrk65ubbKkfpd+ X-Received: by 10.14.111.9 with SMTP id v9mr26790113eeg.35.1377531408967; Mon, 26 Aug 2013 08:36:48 -0700 (PDT) Received: from tn-HP3-PC.semihalf.com (cardhu.semihalf.com. [213.17.239.108]) by mx.google.com with ESMTPSA id i1sm22244200eeg.0.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 26 Aug 2013 08:36:48 -0700 (PDT) From: Tomasz Nowicki To: linaro-acpi@lists.linaro.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] irq, gic: Add interrupt priority to the GIC driver using already existing infrastructure. Date: Mon, 26 Aug 2013 17:36:25 +0200 Message-Id: <1377531385-19369-4-git-send-email-tomasz.nowicki@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377531385-19369-1-git-send-email-tomasz.nowicki@linaro.org> References: <1377531385-19369-1-git-send-email-tomasz.nowicki@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130826_113710_893221_EDADBB3A X-CRM114-Status: GOOD ( 14.61 ) X-Spam-Score: -2.6 (--) Cc: tomasz.nowicki@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Couple of notes: o new handler has been added irq_set_priority o this could be an example of how to map generic priority level to architecture priority value (see comments in code) Signed-off-by: Tomasz Nowicki --- drivers/irqchip/irq-gic.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 13b2849..97e919f 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -93,6 +94,19 @@ struct irq_chip gic_arch_extn = { .irq_set_wake = NULL, }; +/* + * Map generic interrupt priority levels (irqpriority_t) to GIC_DIST_PRI + * register value. Value should be mapped using table index assignment: + * [priority level] = which allow us to be compatible + * in case of irqpriority_t (see include/linux/irqpriority.h) further + * modification. + */ +static unsigned int priority_map [IRQP_LEVELS_NR] = { + [IRQP_HIGH] = 0x00, + [IRQP_DEFAULT] = 0xa0, + [IRQP_LOW] = 0xe0, +}; + #ifndef MAX_GIC_NR #define MAX_GIC_NR 1 #endif @@ -332,12 +346,30 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) chained_irq_exit(chip, desc); } +int gic_set_priority(struct irq_data *data, irqpriority_t priority) +{ + unsigned int hw_irq = gic_irq(data); + u32 cur_priority; + + if (hw_irq < 32) + return -EINVAL; + + raw_spin_lock(&irq_controller_lock); + cur_priority = readl_relaxed(gic_dist_base(data) + GIC_DIST_PRI + (hw_irq / 4) * 4); + cur_priority &= ~(0xff << (hw_irq % 4)); + cur_priority |= priority_map[priority] << (hw_irq % 4); + writel_relaxed(cur_priority, gic_dist_base(data) + GIC_DIST_PRI + (hw_irq / 4) * 4); + raw_spin_unlock(&irq_controller_lock); + return 0; +} + static struct irq_chip gic_chip = { .name = "GIC", .irq_mask = gic_mask_irq, .irq_unmask = gic_unmask_irq, .irq_eoi = gic_eoi_irq, .irq_set_type = gic_set_type, + .irq_set_priority = gic_set_priority, .irq_retrigger = gic_retrigger, #ifdef CONFIG_SMP .irq_set_affinity = gic_set_affinity,