From patchwork Mon Aug 26 17:09:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2849739 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 35D43BF546 for ; Mon, 26 Aug 2013 18:01:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DD0B2201B5 for ; Mon, 26 Aug 2013 18:01:00 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C04D20148 for ; Mon, 26 Aug 2013 18:00:59 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VE0LF-0006IU-Rr; Mon, 26 Aug 2013 17:12:39 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VE0KS-0004ux-3A; Mon, 26 Aug 2013 17:11:48 +0000 Received: from mailout3.w1.samsung.com ([210.118.77.13]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VE0J6-0004iq-QQ for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2013 17:10:28 +0000 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MS500NELEC81BD0@mailout3.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2013 18:09:52 +0100 (BST) X-AuditID: cbfec7f4-b7f0a6d000007b1b-dd-521b8be020d5 Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id FE.24.31515.0EB8B125; Mon, 26 Aug 2013 18:09:52 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MS500C4SEC419A0@eusync1.samsung.com>; Mon, 26 Aug 2013 18:09:52 +0100 (BST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 10/16] clk: samsung: pll: Add support for rate configuration of PLL45xx Date: Mon, 26 Aug 2013 19:09:05 +0200 Message-id: <1377536951-9307-11-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.3.2 In-reply-to: <1377536951-9307-1-git-send-email-t.figa@samsung.com> References: <1377536951-9307-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrELMWRmVeSWpSXmKPExsVy+t/xy7oPuqWDDL79Y7eY91nWYv6Rc6wW Z5cdZLPof7OQ1aJ3wVU2i7NNb9gtNj2+xmox4/w+Joul1y8yWTydcJHNYsL0tSwWh1ccYLJ4 dbCNxWL9jNcsFps3TWW2ODZjCaNF+9+9bBZzpr9jchDyWDNvDaPHgs9X2D1mN1xk8bjc18vk cefaHjaPd+fOsXtsXlLv0bdlFaPH501yHhvnhgZwRXHZpKTmZJalFunbJXBlvLt+kbngok7F 64l/GRsY56p0MXJySAiYSDR0XGWFsMUkLtxbz9bFyMUhJLCUUeLa6klQTh+TROuvE+wgVWwC ahKfGx6xgdgiAqoSn9sWsIMUMQssY5W4fmk5WEJYIEai5f5lsLEsQEXPGpuZQGxeASeJr4v3 M0GsU5BY9mUtcxcjBwcnUHzf/wwQU0jAUWJyt+AERt4FjAyrGEVTS5MLipPScw31ihNzi0vz 0vWS83M3MULC/csOxsXHrA4xCnAwKvHwPmiRDhJiTSwrrsw9xCjBwawkwsuRChTiTUmsrEot yo8vKs1JLT7EyMTBKdXAyMe929z67NVU4Ub3DyIr9aaU9rxYI/v1YtTKWUE7ru6bO7/3eJfm +f/XbctTtm1J/ps/YVJyydFPorWbTZJd224xTWWK55bIfTLzwpp9K25KCW/znGpx6l0a1674 k3nSXT5Fpl21Ld0ZBbuT2l18OQoMRQ8Z9jjPW5J/+d876SgzA5sZa+bpKbEUZyQaajEXFScC AJ+47nlVAgAA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130826_131025_008061_C9FB1DBD X-CRM114-Status: GOOD ( 18.30 ) X-Spam-Score: -9.3 (---------) Cc: Mark Rutland , devicetree@vger.kernel.org, Yadwinder Singh Brar , Kukjin Kim , Mike Turquette , Pawel Moll , Stephen Warren , Tomasz Figa , Daniel Lezcano , Doug Anderson , Rob Herring , Kyungmin Park , Thomas Abraham , Kumar Gala , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Tushar Behera X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch implements round_rate and set_rate callbacks of PLL45xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-pll.c | 110 +++++++++++++++++++++++++++++++++++++++++- drivers/clk/samsung/clk-pll.h | 10 ++++ 2 files changed, 119 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b0398d2..052fc37 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -10,9 +10,12 @@ */ #include +#include #include "clk.h" #include "clk-pll.h" +#define PLL_TIMEOUT_MS 10 + struct samsung_clk_pll { struct clk_hw hw; void __iomem *lock_reg; @@ -272,13 +275,20 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = { /* * PLL45xx Clock Type */ +#define PLL4502_LOCK_FACTOR 400 +#define PLL4508_LOCK_FACTOR 240 #define PLL45XX_MDIV_MASK (0x3FF) #define PLL45XX_PDIV_MASK (0x3F) #define PLL45XX_SDIV_MASK (0x7) +#define PLL45XX_AFC_MASK (0x1F) #define PLL45XX_MDIV_SHIFT (16) #define PLL45XX_PDIV_SHIFT (8) #define PLL45XX_SDIV_SHIFT (0) +#define PLL45XX_AFC_SHIFT (0) + +#define PLL45XX_ENABLE BIT(31) +#define PLL45XX_LOCKED BIT(29) static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -301,8 +311,101 @@ static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, return (unsigned long)fvco; } +static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1, + const struct samsung_pll_rate_table *rate) +{ + u32 old_mdiv, old_pdiv, old_afc; + + old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; + old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; + old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK; + + return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv + || old_afc != rate->afc); +} + +static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 con0, con1; + ktime_t start; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + con0 = __raw_readl(pll->con_reg); + con1 = __raw_readl(pll->con_reg + 0x4); + + if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { + /* If only s change, change just s value only*/ + con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); + con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; + __raw_writel(con0, pll->con_reg); + + return 0; + } + + /* Set PLL PMS values. */ + con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | + (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) | + (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT)); + con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | + (rate->pdiv << PLL45XX_PDIV_SHIFT) | + (rate->sdiv << PLL45XX_SDIV_SHIFT); + + /* Set PLL AFC value. */ + con1 = __raw_readl(pll->con_reg + 0x4); + con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); + con1 |= (rate->afc << PLL45XX_AFC_SHIFT); + + /* Set PLL lock time. */ + switch (pll->type) { + case pll_4502: + __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); + break; + case pll_4508: + __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); + break; + default: + break; + }; + + /* Set new configuration. */ + __raw_writel(con1, pll->con_reg + 0x4); + __raw_writel(con0, pll->con_reg); + + /* Wait for locking. */ + start = ktime_get(); + while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) { + ktime_t delta = ktime_sub(ktime_get(), start); + + if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { + pr_err("%s: could not lock PLL %s\n", + __func__, __clk_get_name(hw->clk)); + return -EFAULT; + } + + cpu_relax(); + } + + return 0; +} + static const struct clk_ops samsung_pll45xx_clk_ops = { .recalc_rate = samsung_pll45xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll45xx_set_rate, +}; + +static const struct clk_ops samsung_pll45xx_clk_min_ops = { + .recalc_rate = samsung_pll45xx_recalc_rate, }; /* @@ -680,9 +783,14 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, init.ops = &samsung_pll35xx_clk_ops; break; case pll_4500: + init.ops = &samsung_pll45xx_clk_min_ops; + break; case pll_4502: case pll_4508: - init.ops = &samsung_pll45xx_clk_ops; + if (!pll->rate_table) + init.ops = &samsung_pll45xx_clk_min_ops; + else + init.ops = &samsung_pll45xx_clk_ops; break; /* clk_ops for 36xx and 2650 are similar */ case pll_36xx: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index f3faf24..aa8cc15 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -39,6 +39,15 @@ enum samsung_pll_type { .kdiv = (_k), \ } +#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .afc = (_afc), \ + } + /* NOTE: Rate table should be kept sorted in descending order. */ struct samsung_pll_rate_table { @@ -47,6 +56,7 @@ struct samsung_pll_rate_table { unsigned int mdiv; unsigned int sdiv; unsigned int kdiv; + unsigned int afc; }; enum pll46xx_type {