From patchwork Wed Aug 28 13:10:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2850790 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DC1169F271 for ; Wed, 28 Aug 2013 14:06:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A17B420523 for ; Wed, 28 Aug 2013 14:06:51 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DAC7A20520 for ; Wed, 28 Aug 2013 14:06:49 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VEfZJ-000723-BH; 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Wed, 28 Aug 2013 06:12:14 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id vz4sm33857518pab.11.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 28 Aug 2013 06:12:13 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, john.stultz@linaro.org, mturquette@linaro.org, grant.likely@linaro.org, mark.rutland@arm.com, khilman@linaro.org, swarren@wwwdotorg.org, shaojie.sun@linaro.org Subject: [PATCH v9 6/7] ARM: hi3xxx: add smp support Date: Wed, 28 Aug 2013 21:10:53 +0800 Message-Id: <1377695454-29109-7-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1377695454-29109-1-git-send-email-haojian.zhuang@linaro.org> References: <1377695454-29109-1-git-send-email-haojian.zhuang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130828_091236_961189_7D44D1A8 X-CRM114-Status: GOOD ( 20.51 ) X-Spam-Score: -2.6 (--) Cc: Zhangfei Gao , Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Zhangfei Gao Enable SMP support on hi3xxx platform Signed-off-by: Zhangfei Gao Tested-by: Zhang Mingjun Tested-by: Li Xin Signed-off-by: Haojian Zhuang --- .../bindings/arm/hisilicon/hisilicon.txt | 50 +++++++++++++++++ arch/arm/boot/dts/hi3620-clk.dtsi | 4 ++ arch/arm/boot/dts/hi3620.dtsi | 27 +++++++++ arch/arm/mach-hi3xxx/Kconfig | 2 + arch/arm/mach-hi3xxx/Makefile | 3 +- arch/arm/mach-hi3xxx/core.h | 13 +++++ arch/arm/mach-hi3xxx/hi3xxx.c | 5 ++ arch/arm/mach-hi3xxx/platsmp.c | 43 ++++++++++++++ arch/arm/mach-hi3xxx/system.c | 65 ++++++++++++++++++++++ 9 files changed, 211 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-hi3xxx/core.h create mode 100644 arch/arm/mach-hi3xxx/platsmp.c create mode 100644 arch/arm/mach-hi3xxx/system.c diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 3be60c8..1462903 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -8,3 +8,53 @@ Required root node properties: Hi4511 Board Required root node properties: - compatible = "hisilicon,hi3620-hi4511"; + + +Hisilicon system controller + +Required properties: +- compatible : "hisilicon,sysctrl" +- reg : Register address and size + +Optional properties: +- smp-off : offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go +- resume-off : offset in sysctrl for notifying cpu0 when resume +- reboot-off : offset in sysctrl for system reboot + +Example: + + /* for Hi3716 */ + sysctrl: system-controller@f8000000 { + compatible = "hisilicon,sysctrl"; + reg = <0xf8000000 0x1000>; + smp-off = <0xc0>; + reboot-off = <0x4>; + }; + + /* for Hi3620 */ + sysctrl: system-controller@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp-off = <0x31c>; + resume-off = <0x308>; + reboot-off = <0x4>; + }; + +Hi3716 cpuctrl register +Hi3716 specific cpuctrl register, control power & clock of cpu and module. + +Required properties: +- compatible : "hisilicon,hi3716-cpuctrl" +- reg : register address and size + +Example: + + /* for Hi3716 */ + cpuctrl@f8a22000 { + compatible = "hisilicon,hi3716-cpuctrl"; + reg = <0xf8a22000 0x2000>; + }; diff --git a/arch/arm/boot/dts/hi3620-clk.dtsi b/arch/arm/boot/dts/hi3620-clk.dtsi index 78307c6..78a2a8bf 100644 --- a/arch/arm/boot/dts/hi3620-clk.dtsi +++ b/arch/arm/boot/dts/hi3620-clk.dtsi @@ -102,6 +102,10 @@ #address-cells = <1>; #size-cells = <0>; + smp-off = <0x31c>; + resume-off = <0x308>; + reboot-off = <0x4>; + timer0_mux: timer0_mux { compatible = "hisilicon,clk-mux"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index e05c65c..03c816c 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -34,6 +34,27 @@ reg = <0x0>; next-level-cache = <&L2>; }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; }; amba { @@ -110,6 +131,12 @@ status = "disabled"; }; + timer5: timer@fc000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfc000600 0x20>; + interrupts = <1 13 0xf01>; + }; + uart0: uart@fcb00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xfcb00000 0x1000>; diff --git a/arch/arm/mach-hi3xxx/Kconfig b/arch/arm/mach-hi3xxx/Kconfig index 68bd26c..d2e7d57 100644 --- a/arch/arm/mach-hi3xxx/Kconfig +++ b/arch/arm/mach-hi3xxx/Kconfig @@ -6,6 +6,8 @@ config ARCH_HI3xxx select CACHE_L2X0 select CLKSRC_OF select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU + select HAVE_SMP select PINCTRL select PINCTRL_SINGLE help diff --git a/arch/arm/mach-hi3xxx/Makefile b/arch/arm/mach-hi3xxx/Makefile index d68ebb3..0917f1c 100644 --- a/arch/arm/mach-hi3xxx/Makefile +++ b/arch/arm/mach-hi3xxx/Makefile @@ -2,4 +2,5 @@ # Makefile for Hisilicon Hi36xx/Hi37xx processors line # -obj-y += hi3xxx.o +obj-y += hi3xxx.o system.o +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-hi3xxx/core.h b/arch/arm/mach-hi3xxx/core.h new file mode 100644 index 0000000..3a9c50a --- /dev/null +++ b/arch/arm/mach-hi3xxx/core.h @@ -0,0 +1,13 @@ +#ifndef __HISILICON_CORE_H +#define __HISILICON_CORE_H + +#include + +extern void hs_set_cpu_jump(int cpu, void *jump_addr); +extern int hs_get_cpu_jump(int cpu); +extern void secondary_startup(void); +extern void hs_map_io(void); +extern void hs_restart(enum reboot_mode, const char *cmd); +extern struct smp_operations hs_smp_ops; + +#endif diff --git a/arch/arm/mach-hi3xxx/hi3xxx.c b/arch/arm/mach-hi3xxx/hi3xxx.c index e7c54bc..567a0d5 100644 --- a/arch/arm/mach-hi3xxx/hi3xxx.c +++ b/arch/arm/mach-hi3xxx/hi3xxx.c @@ -19,8 +19,11 @@ #include #include +#include "core.h" + static void __init hi3xxx_timer_init(void) { + hs_map_io(); of_clk_init(NULL); clocksource_of_init(); } @@ -33,4 +36,6 @@ static const char *hs_compat[] __initdata = { DT_MACHINE_START(HI3xxx, "Hisilicon Hi36xx/Hi37xx (Flattened Device Tree)") .init_time = hi3xxx_timer_init, .dt_compat = hs_compat, + .smp = smp_ops(hs_smp_ops), + .restart = hs_restart, MACHINE_END diff --git a/arch/arm/mach-hi3xxx/platsmp.c b/arch/arm/mach-hi3xxx/platsmp.c new file mode 100644 index 0000000..a76a3cc --- /dev/null +++ b/arch/arm/mach-hi3xxx/platsmp.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * Based on platsmp.c, Copyright (C) 2002 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ +#include +#include +#include + +#include "core.h" + +static void __init hs_smp_prepare_cpus(unsigned int max_cpus) +{ + unsigned long base; + void __iomem *scu_base; + + if (scu_a9_has_base()) { + base = scu_a9_get_base(); + scu_base = ioremap(base, SZ_4K); + if (!scu_base) { + pr_err("ioremap(scu_base) failed\n"); + return; + } + scu_enable(scu_base); + iounmap(scu_base); + } +} + +static int hs_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + hs_set_cpu_jump(cpu, secondary_startup); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + return 0; +} + +struct smp_operations hs_smp_ops __initdata = { + .smp_prepare_cpus = hs_smp_prepare_cpus, + .smp_boot_secondary = hs_boot_secondary, +}; diff --git a/arch/arm/mach-hi3xxx/system.c b/arch/arm/mach-hi3xxx/system.c new file mode 100644 index 0000000..1276398 --- /dev/null +++ b/arch/arm/mach-hi3xxx/system.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ +#include +#include +#include + +#include +#include + +#include "core.h" + +static void __iomem *hs_sysctrl_base; +static int hs_smp_reg; +static int hs_resume_reg; +static int hs_reboot_reg; + +void hs_map_io(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); + if (np) { + hs_sysctrl_base = of_iomap(np, 0); + if (!hs_sysctrl_base) + pr_err("of_iomap(sysctrl_base) failed\n"); + of_property_read_u32(np, "smp-off", &hs_smp_reg); + of_property_read_u32(np, "resume-off", &hs_resume_reg); + of_property_read_u32(np, "reboot-off", &hs_reboot_reg); + } +} + +void hs_set_cpu_jump(int cpu, void *jump_addr) +{ + int offset = hs_smp_reg; + + cpu = cpu_logical_map(cpu); + if (cpu > 0) + offset += 0x04 * (cpu - 1); + writel_relaxed(virt_to_phys(jump_addr), hs_sysctrl_base + offset); +} + +int hs_get_cpu_jump(int cpu) +{ + int offset = hs_smp_reg; + + cpu = cpu_logical_map(cpu); + if (cpu > 0) + offset += 0x04 * (cpu - 1); + return readl_relaxed(hs_sysctrl_base + offset); +} + +void hs_restart(enum reboot_mode mode, const char *cmd) +{ + writel_relaxed(0xdeadbeef, hs_sysctrl_base + hs_reboot_reg); + + while (1) + cpu_do_idle(); +} +