From patchwork Fri Aug 30 02:07:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 2851715 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C0B8AC0AB5 for ; Fri, 30 Aug 2013 02:15:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D4462200E9 for ; Fri, 30 Aug 2013 02:15:42 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CCC70200CC for ; Fri, 30 Aug 2013 02:15:41 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VFEEi-0007Lp-8E; Fri, 30 Aug 2013 02:14:56 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VFEER-0001BY-3U; Fri, 30 Aug 2013 02:14:39 +0000 Received: from mail-db9lp0251.outbound.messaging.microsoft.com ([213.199.154.251] helo=db9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VFEDd-000126-Qz; Fri, 30 Aug 2013 02:13:56 +0000 Received: from mail33-db9-R.bigfish.com (10.174.16.227) by DB9EHSOBE024.bigfish.com (10.174.14.87) with Microsoft SMTP Server id 14.1.225.22; Fri, 30 Aug 2013 02:13:32 +0000 Received: from mail33-db9 (localhost [127.0.0.1]) by mail33-db9-R.bigfish.com (Postfix) with ESMTP id 9160260071; Fri, 30 Aug 2013 02:13:32 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail33-db9 (localhost.localdomain [127.0.0.1]) by mail33-db9 (MessageSwitch) id 137782881137582_1279; Fri, 30 Aug 2013 02:13:31 +0000 (UTC) Received: from DB9EHSMHS006.bigfish.com (unknown [10.174.16.248]) by mail33-db9.bigfish.com (Postfix) with ESMTP id ED3C93E0059; Fri, 30 Aug 2013 02:13:30 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB9EHSMHS006.bigfish.com (10.174.14.16) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 30 Aug 2013 02:13:30 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.146.2; Fri, 30 Aug 2013 02:13:29 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r7U2D7jT023133; Thu, 29 Aug 2013 19:13:24 -0700 From: Huang Shijie To: Subject: [PATCH v3 3/8] mtd: m25p80: add the quad-read support Date: Fri, 30 Aug 2013 10:07:24 +0800 Message-ID: <1377828449-18912-4-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1377828449-18912-1-git-send-email-b32955@freescale.com> References: <1377828449-18912-1-git-send-email-b32955@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130829_221350_316276_1CF32111 X-CRM114-Status: GOOD ( 21.42 ) X-Spam-Score: -1.9 (-) Cc: devicetree@vger.kernel.org, computersforpeace@gmail.com, b44548@freescale.com, dedekind1@gmail.com, linux-doc@vger.kernel.org, b18965@freescale.com, linux-spi@vger.kernel.org, Huang Shijie , linux-mtd@lists.infradead.org, kernel@pengutronix.de, lznuaa@gmail.com, shawn.guo@linaro.org, dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the quad read support: (1) Add the relative commands: OPCODE_QIOR, OPCODE_4QIOR, OPCODE_RDCR, also add the relative macro for the Configuartion Register. (2) add the "m25p,quad-read" property for the m25p80 driver If the dts has the "m25p,quad-read" property, the kernel will set the Quad bit of the configuration register, and when the setting suceedes, we will set the read opcode with the right spi nor command. Signed-off-by: Huang Shijie --- Documentation/devicetree/bindings/mtd/m25p80.txt | 5 ++ drivers/mtd/devices/m25p80.c | 62 ++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 6 ++ 3 files changed, 73 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt b/Documentation/devicetree/bindings/mtd/m25p80.txt index 6d3d576..b33313f 100644 --- a/Documentation/devicetree/bindings/mtd/m25p80.txt +++ b/Documentation/devicetree/bindings/mtd/m25p80.txt @@ -17,6 +17,11 @@ Optional properties: Refer to your chips' datasheet to check if this is supported by your chip. +- m25p,quad-read : Use the "quad read" opcode to read data from the chip instead + of the usual "read" opcode. This opcode is not supported by + all chips and support for it can not be detected at runtime. + Refer to your chips' datasheet to check if this is supported + by your chip. Example: flash: m25p80@0 { diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index cae419e..0645c9f 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -103,6 +103,40 @@ static int write_sr(struct m25p *flash, u8 val) } /* + * Read the configuration register, returning its value in the location + * Return the configuration register value. + * Returns negative if error occurred. + */ +static int read_cr(struct m25p *flash) +{ + u8 code = OPCODE_RDCR; + int ret; + u8 val; + + ret = spi_write_then_read(flash->spi, &code, 1, &val, 1); + if (ret < 0) { + dev_err(&flash->spi->dev, "error %d reading CR\n", ret); + return ret; + } + return val; +} + +/* + * Write status register and configuration register with 2 bytes + * The first byte will be written to the status register, while the second byte + * will be written to the configuration register. + * Returns negative if error occurred. + */ +static int write_sr_cr(struct m25p *flash, u16 val) +{ + flash->command[0] = OPCODE_WRSR; + flash->command[1] = val & 0xff; + flash->command[2] = (val >> 8); + + return spi_write(flash->spi, flash->command, 3); +} + +/* * Set write enable latch with Write Enable command. * Returns negative if error occurred. */ @@ -874,6 +908,31 @@ static const struct spi_device_id *jedec_probe(struct spi_device *spi) return ERR_PTR(-ENODEV); } +static void m25p80_check_quad_read(struct m25p *flash, struct device_node *np) +{ + int ret; + int sr_cr; + + if (of_property_read_bool(np, "m25p,quad-read")) { + /* The configuration register is set by the second byte. */ + sr_cr = CR_QUAD << 8; + + /* Write the QUAD bit to the Configuration Register. */ + write_enable(flash); + if (write_sr_cr(flash, sr_cr)) + return; + + /* read back and check it */ + ret = read_cr(flash); + if (!(ret > 0 && (ret & CR_QUAD))) + return; + + if (flash->mtd.size <= SZ_16M) + flash->read_opcode = OPCODE_QIOR; + else + flash->read_opcode = OPCODE_4QIOR; + } +} /* * board specific setup should have ensured the SPI clock used here @@ -1048,6 +1107,9 @@ static int m25p_probe(struct spi_device *spi) flash->addr_width = 3; } + /* Try to enable the Quad Read */ + m25p80_check_quad_read(flash, np); + dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name, (long long)flash->mtd.size >> 10); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index f2637b9..e6c3309 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -40,6 +40,9 @@ /* Used for Spansion flashes only. */ #define OPCODE_BRWR 0x17 /* Bank register write */ +#define OPCODE_QIOR 0xeb /* Quad read */ +#define OPCODE_4QIOR 0xec /* Quad read (4-byte)*/ +#define OPCODE_RDCR 0x35 /* Read configuration register */ /* Status Register bits. */ #define SR_WIP 1 /* Write in progress */ @@ -50,4 +53,7 @@ #define SR_BP2 0x10 /* Block protect 2 */ #define SR_SRWD 0x80 /* SR write protect */ +/* Configuration Register bits. */ +#define CR_QUAD 0x2 /* Quad I/O */ + #endif /* __LINUX_MTD_SPI_NOR_H */