From patchwork Fri Aug 30 02:07:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 2851718 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E8DBB9F2F4 for ; Fri, 30 Aug 2013 02:17:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E8ECE2018D for ; Fri, 30 Aug 2013 02:17:03 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EC3D12017A for ; Fri, 30 Aug 2013 02:17:02 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VFEFQ-0007oj-HT; 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Fri, 30 Aug 2013 02:13:35 +0000 (UTC) Received: from DB9EHSMHS028.bigfish.com (unknown [10.174.16.228]) by mail112-db9.bigfish.com (Postfix) with ESMTP id 8FBAF420074; Fri, 30 Aug 2013 02:13:35 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB9EHSMHS028.bigfish.com (10.174.14.38) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 30 Aug 2013 02:13:35 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.146.2; Fri, 30 Aug 2013 02:13:33 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r7U2D7jU023133; Thu, 29 Aug 2013 19:13:29 -0700 From: Huang Shijie To: Subject: [PATCH v3 4/8] mtd: m25p80: add the DDR quad-read support Date: Fri, 30 Aug 2013 10:07:25 +0800 Message-ID: <1377828449-18912-5-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1377828449-18912-1-git-send-email-b32955@freescale.com> References: <1377828449-18912-1-git-send-email-b32955@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130829_221354_876924_2BFAE84B X-CRM114-Status: GOOD ( 15.26 ) X-Spam-Score: -1.9 (-) Cc: devicetree@vger.kernel.org, computersforpeace@gmail.com, b44548@freescale.com, dedekind1@gmail.com, linux-doc@vger.kernel.org, b18965@freescale.com, linux-spi@vger.kernel.org, Huang Shijie , linux-mtd@lists.infradead.org, kernel@pengutronix.de, lznuaa@gmail.com, shawn.guo@linaro.org, dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the DDR quad read support by: (1) Add the relative commands: OPCODE_DDRQIOR, OPCODE_4DDRQIOR (2) add the "m25p,ddr-quad-read" property for the m25p80 driver If the dts has the "m25p,ddr-quad-read" property, the kernel will set the Quad bit of the configuration register, and when the setting suceedes, we will set the read opcode with the right spi nor command. Signed-off-by: Huang Shijie --- Documentation/devicetree/bindings/mtd/m25p80.txt | 5 +++++ drivers/mtd/devices/m25p80.c | 21 ++++++++++++++++----- include/linux/mtd/spi-nor.h | 2 ++ 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt b/Documentation/devicetree/bindings/mtd/m25p80.txt index b33313f..a01c6b7 100644 --- a/Documentation/devicetree/bindings/mtd/m25p80.txt +++ b/Documentation/devicetree/bindings/mtd/m25p80.txt @@ -22,6 +22,11 @@ Optional properties: all chips and support for it can not be detected at runtime. Refer to your chips' datasheet to check if this is supported by your chip. +- m25p,ddr-quad-read : Use the "ddr quad read" opcode to read data from the chip + instead of the usual "read" opcode. This opcode is not + supported by all chips and support for it can not be detected + at runtime. Refer to your chips' datasheet to check if this + is supported by your chip. Example: flash: m25p80@0 { diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 0645c9f..32ccdc7 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -913,7 +913,8 @@ static void m25p80_check_quad_read(struct m25p *flash, struct device_node *np) int ret; int sr_cr; - if (of_property_read_bool(np, "m25p,quad-read")) { + if (of_property_read_bool(np, "m25p,quad-read") + || of_property_read_bool(np, "m25p,ddr-quad-read")) { /* The configuration register is set by the second byte. */ sr_cr = CR_QUAD << 8; @@ -927,10 +928,20 @@ static void m25p80_check_quad_read(struct m25p *flash, struct device_node *np) if (!(ret > 0 && (ret & CR_QUAD))) return; - if (flash->mtd.size <= SZ_16M) - flash->read_opcode = OPCODE_QIOR; - else - flash->read_opcode = OPCODE_4QIOR; + if (of_property_read_bool(np, "m25p,quad-read")) { + if (flash->mtd.size <= SZ_16M) + flash->read_opcode = OPCODE_QIOR; + else + flash->read_opcode = OPCODE_4QIOR; + return; + } + + if (of_property_read_bool(np, "m25p,ddr-quad-read")) { + if (flash->mtd.size <= SZ_16M) + flash->read_opcode = OPCODE_DDRQIOR; + else + flash->read_opcode = OPCODE_4DDRQIOR; + } } } diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e6c3309..a985336 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -42,6 +42,8 @@ #define OPCODE_BRWR 0x17 /* Bank register write */ #define OPCODE_QIOR 0xeb /* Quad read */ #define OPCODE_4QIOR 0xec /* Quad read (4-byte)*/ +#define OPCODE_DDRQIOR 0xed /* DDR Quad read */ +#define OPCODE_4DDRQIOR 0xee /* DDR Quad read (4-byte)*/ #define OPCODE_RDCR 0x35 /* Read configuration register */ /* Status Register bits. */