| Message ID | 1378740833-4883-2-git-send-email-dinguyen@altera.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi! > From: Dinh Nguyen <dinguyen@altera.com> > > Add functionality in the System Manager to set the SDR settings for the > SD/MMC IP. > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > Cc: Pavel Machek <pavel@denx.de> > +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(void) > +{ > + struct device_node *np; > + u32 timing[2]; > + u32 hs_timing; > + > + np = of_find_compatible_node(NULL, NULL, "altr,socfpga-dw-mshc"); > + of_property_read_u32_array(np, "samsung,dw-mshc-sdr-timing", timing, 2); > + hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); > + writel(hs_timing, sys_manager_base_addr + SYSMGR_SDMMCGRP_CTRL_OFFSET); > +} > +EXPORT_SYMBOL(socfpga_sysmgr_set_dwmmc_drvsel_smpsel); To get the abstraction right, would it make sense to have timing parameters as arguments to socfpga_sysmgr_set_dwmmc_drvsel_smpsel(), so that sysmgr code is not walking MMC's device tree directly? Thanks, Pavel
Hi Dinh, On Sat, Sep 14 2013, Pavel Machek wrote: >> From: Dinh Nguyen <dinguyen@altera.com> >> >> Add functionality in the System Manager to set the SDR settings for the >> SD/MMC IP. >> >> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> >> Cc: Pavel Machek <pavel@denx.de> > >> +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(void) >> +{ >> + struct device_node *np; >> + u32 timing[2]; >> + u32 hs_timing; >> + >> + np = of_find_compatible_node(NULL, NULL, "altr,socfpga-dw-mshc"); >> + of_property_read_u32_array(np, "samsung,dw-mshc-sdr-timing", timing, 2); >> + hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); >> + writel(hs_timing, sys_manager_base_addr + SYSMGR_SDMMCGRP_CTRL_OFFSET); >> +} >> +EXPORT_SYMBOL(socfpga_sysmgr_set_dwmmc_drvsel_smpsel); > > To get the abstraction right, would it make sense to have timing > parameters as arguments to socfpga_sysmgr_set_dwmmc_drvsel_smpsel(), > so that sysmgr code is not walking MMC's device tree directly? I think this review comment from Pavel is still open, please reply. Thanks, - Chris.
Hi Chris, On Sep 25, 2013, at 8:50 PM, Chris Ball wrote: > Hi Dinh, > > On Sat, Sep 14 2013, Pavel Machek wrote: >>> From: Dinh Nguyen <dinguyen@altera.com> >>> >>> Add functionality in the System Manager to set the SDR settings for the >>> SD/MMC IP. >>> >>> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> >>> Cc: Pavel Machek <pavel@denx.de> >> >>> +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(void) >>> +{ >>> + struct device_node *np; >>> + u32 timing[2]; >>> + u32 hs_timing; >>> + >>> + np = of_find_compatible_node(NULL, NULL, "altr,socfpga-dw-mshc"); >>> + of_property_read_u32_array(np, "samsung,dw-mshc-sdr-timing", timing, 2); >>> + hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); >>> + writel(hs_timing, sys_manager_base_addr + SYSMGR_SDMMCGRP_CTRL_OFFSET); >>> +} >>> +EXPORT_SYMBOL(socfpga_sysmgr_set_dwmmc_drvsel_smpsel); >> >> To get the abstraction right, would it make sense to have timing >> parameters as arguments to socfpga_sysmgr_set_dwmmc_drvsel_smpsel(), >> so that sysmgr code is not walking MMC's device tree directly? > > I think this review comment from Pavel is still open, please reply. I sent a Rev 2 that addresses this comment on 9/23. Let me know if I need to resend it in case you missed it. Thanks, Dinh > Thanks, > > - Chris. > -- > Chris Ball <cjb@laptop.org> <http://printf.net/>
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 6dd7a93..e4ff8b9 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -2,5 +2,5 @@ # Makefile for the linux kernel. # -obj-y := socfpga.o +obj-y := socfpga.o system_mgr.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 572b8f7..b05fa6a 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -44,4 +44,10 @@ extern unsigned long cpu1start_addr; #define SOCFPGA_SCU_VIRT_BASE 0xfffec000 +/* SDMMC Group for System Manager defines */ +#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 +#define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) + #endif diff --git a/arch/arm/mach-socfpga/system_mgr.c b/arch/arm/mach-socfpga/system_mgr.c new file mode 100644 index 0000000..c69a854 --- /dev/null +++ b/arch/arm/mach-socfpga/system_mgr.c @@ -0,0 +1,32 @@ +/* + * Copyright Altera Corporation (C) 2013. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <linux/of_platform.h> +#include <asm/mach/map.h> + +#include "core.h" + +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(void) +{ + struct device_node *np; + u32 timing[2]; + u32 hs_timing; + + np = of_find_compatible_node(NULL, NULL, "altr,socfpga-dw-mshc"); + of_property_read_u32_array(np, "samsung,dw-mshc-sdr-timing", timing, 2); + hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); + writel(hs_timing, sys_manager_base_addr + SYSMGR_SDMMCGRP_CTRL_OFFSET); +} +EXPORT_SYMBOL(socfpga_sysmgr_set_dwmmc_drvsel_smpsel);