From patchwork Mon Sep 9 15:33:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2862011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A91839F2D6 for ; Mon, 9 Sep 2013 15:35:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5BCEE201BF for ; Mon, 9 Sep 2013 15:35:11 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D3AB020138 for ; Mon, 9 Sep 2013 15:35:09 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VJ3UD-0008JH-1K; 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envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail167-co1 (localhost.localdomain [127.0.0.1]) by mail167-co1 (MessageSwitch) id 1378740843704795_18091; Mon, 9 Sep 2013 15:34:03 +0000 (UTC) Received: from CO1EHSMHS023.bigfish.com (unknown [10.243.78.240]) by mail167-co1.bigfish.com (Postfix) with ESMTP id 9C75EC0004B; Mon, 9 Sep 2013 15:34:03 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by CO1EHSMHS023.bigfish.com (10.243.66.33) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 9 Sep 2013 15:34:02 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Mon, 9 Sep 2013 08:23:00 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.121]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r89FXtrw022776; Mon, 9 Sep 2013 08:34:00 -0700 (PDT) From: To: Subject: [PATCH 2/3] mmc: dw_mmc-socfpga: Clean up SOCFPGA platform specific functionality Date: Mon, 9 Sep 2013 10:33:52 -0500 Message-ID: <1378740833-4883-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1378740833-4883-1-git-send-email-dinguyen@altera.com> References: <1378740833-4883-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130909_113427_889583_91AF5450 X-CRM114-Status: GOOD ( 18.82 ) X-Spam-Score: -2.6 (--) Cc: Mark Rutland , devicetree@vger.kernel.org, Arnd Bergmann , Pawel Moll , Stephen Warren , Seungwon Jeon , Pavel Machek , linux-mmc@vger.kernel.org, Rob Herring , Jaehoon Chung , linux-arm-kernel@lists.infradead.org, Olof Johansson , Chris Ball , Dinh Nguyen , Ian Campbell X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The SDR timing registers for the SD/MMC IP block for SOCFPGA is located in the system manager. This system manager IP block is located outside of the SD IP block itself. Therefore, the function to set the SDR timing register should be in the platform specific code so that the SD driver can be autonomous of any future System Manager changes. Also, there is no need for "altr,dw-mshc-ciu-div" as the driver can get the value of the CIU clock from the common clock API. Signed-off-by: Dinh Nguyen Cc: Pavel Machek CC: Arnd Bergmann CC: Olof Johansson Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell Cc: Chris Ball Cc: Jaehoon Chung Cc: Seungwon Jeon Cc: devicetree@vger.kernel.org Cc: linux-mmc@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- drivers/mmc/host/dw_mmc-pltfm.h | 2 +- drivers/mmc/host/dw_mmc-socfpga.c | 63 ++----------------------------------- 2 files changed, 3 insertions(+), 62 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-pltfm.h b/drivers/mmc/host/dw_mmc-pltfm.h index 68e7fd2..682400f 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.h +++ b/drivers/mmc/host/dw_mmc-pltfm.h @@ -16,5 +16,5 @@ extern int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data); extern int dw_mci_pltfm_remove(struct platform_device *pdev); extern const struct dev_pm_ops dw_mci_pltfm_pmops; - +extern void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(void); #endif /* _DW_MMC_PLTFM_H_ */ diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c index 14b5961..924a950 100644 --- a/drivers/mmc/host/dw_mmc-socfpga.c +++ b/drivers/mmc/host/dw_mmc-socfpga.c @@ -24,48 +24,14 @@ #include "dw_mmc.h" #include "dw_mmc-pltfm.h" -#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 -#define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7 -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) - -/* SOCFPGA implementation specific driver private data */ -struct dw_mci_socfpga_priv_data { - u8 ciu_div; /* card interface unit divisor */ - u32 hs_timing; /* bitmask for CIU clock phase shift */ - struct regmap *sysreg; /* regmap for system manager register */ -}; - -static int dw_mci_socfpga_priv_init(struct dw_mci *host) -{ - struct dw_mci_socfpga_priv_data *priv; - - priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) { - dev_err(host->dev, "mem alloc failed for private data\n"); - return -ENOMEM; - } - - priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(priv->sysreg)) { - dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n"); - return PTR_ERR(priv->sysreg); - } - host->priv = priv; - - return 0; -} - static int dw_mci_socfpga_setup_clock(struct dw_mci *host) { struct dw_mci_socfpga_priv_data *priv = host->priv; clk_disable_unprepare(host->ciu_clk); - regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, - priv->hs_timing); + socfpga_sysmgr_set_dwmmc_drvsel_smpsel(); clk_prepare_enable(host->ciu_clk); - host->bus_hz /= (priv->ciu_div + 1); return 0; } @@ -73,37 +39,12 @@ static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr) { struct dw_mci_socfpga_priv_data *priv = host->priv; - if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK) - *cmdr |= SDMMC_CMD_USE_HOLD_REG; -} - -static int dw_mci_socfpga_parse_dt(struct dw_mci *host) -{ - struct dw_mci_socfpga_priv_data *priv = host->priv; - struct device_node *np = host->dev->of_node; - u32 timing[2]; - u32 div = 0; - int ret; - - ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div); - if (ret) - dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1"); - priv->ciu_div = div; - - ret = of_property_read_u32_array(np, - "altr,dw-mshc-sdr-timing", timing, 2); - if (ret) - return ret; - - priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); - return 0; + *cmdr |= SDMMC_CMD_USE_HOLD_REG; } static const struct dw_mci_drv_data socfpga_drv_data = { - .init = dw_mci_socfpga_priv_init, .setup_clock = dw_mci_socfpga_setup_clock, .prepare_command = dw_mci_socfpga_prepare_command, - .parse_dt = dw_mci_socfpga_parse_dt, }; static const struct of_device_id dw_mci_socfpga_match[] = {