| Message ID | 1379436433-24914-1-git-send-email-nm@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tuesday 17 September 2013 12:47 PM, Nishanth Menon wrote: > CNTFREQ isn't pre-programmed on DRA7 just like O5, so provide the > same. Without a valid value arch_timer_init results in div0 crash. s/same/timer frequency via DT > Providing the same is a safer alternative. Above statement won't be necessary. > Cc: R Sricharan <r.sricharan@ti.com> > Cc: Rajendra Nayak <rnayak@ti.com> > Cc: Sourav Poddar <sourav.poddar@ti.com> > Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> > > Signed-off-by: Nishanth Menon <nm@ti.com> > --- > Apart from minor change log fix, Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c01ef76..b478beb 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -50,6 +50,7 @@ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <6144000>; }; gic: interrupt-controller@48211000 {
CNTFREQ isn't pre-programmed on DRA7 just like O5, so provide the same. Without a valid value arch_timer_init results in div0 crash. Providing the same is a safer alternative. Cc: R Sricharan <r.sricharan@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Sourav Poddar <sourav.poddar@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> --- Based on Benoit's for_3.13/dts branch. http://git.kernel.org/cgit/linux/kernel/git/bcousson/linux-omap-dt.git/log/?h=for_3.13/dts Without this patch, div0 error occurs(seen on 3.12-rc1 tag): http://pastebin.com/B2sDauS9 arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+)