From patchwork Wed Sep 18 14:41:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 2907511 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AE4039F23C for ; Wed, 18 Sep 2013 14:57:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7081C201FF for ; Wed, 18 Sep 2013 14:57:44 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0DCE020172 for ; Wed, 18 Sep 2013 14:57:43 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VMJCG-0005wc-4X; Wed, 18 Sep 2013 14:57:40 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VMJCD-0005pk-TX; Wed, 18 Sep 2013 14:57:37 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VMJCA-0005nu-KW for linux-arm-kernel@lists.infradead.org; Wed, 18 Sep 2013 14:57:35 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 18 Sep 2013 07:57:09 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 18 Sep 2013 07:53:52 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 18 Sep 2013 07:53:52 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.298.1; Wed, 18 Sep 2013 07:57:13 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 18 Sep 2013 07:57:13 -0700 Received: from tbergstrom-lnx.nvidia.com (tbergstrom-lnx.nvidia.com [10.21.24.170]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r8IEiJKv008100; Wed, 18 Sep 2013 07:57:10 -0700 (PDT) From: Peter De Schrijver To: Peter De Schrijver Subject: [PATCH 11/12] clk: tegra: introduce common tegra_osc_clk_init Date: Wed, 18 Sep 2013 17:41:03 +0300 Message-ID: <1379515331-19427-12-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty In-Reply-To: <1379515331-19427-1-git-send-email-pdeschrijver@nvidia.com> References: <1379515331-19427-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130918_105734_853174_10E4A1DF X-CRM114-Status: GOOD ( 19.75 ) X-Spam-Score: -2.6 (--) Cc: Prashant Gaikwad , Mike Turquette , Stephen Warren , Thierry Reding , linux-kernel@vger.kernel.org, Paul Walmsley , Joseph Lo , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce a common tegra_osc_clk_init function which handles OSC and pll ref probing and clock registration. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-tegra-osc.c | 81 +++++++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk-tegra114.c | 39 +----------------- drivers/clk/tegra/clk.h | 4 ++ 4 files changed, 88 insertions(+), 37 deletions(-) create mode 100644 drivers/clk/tegra/clk-tegra-osc.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index a02e9a9..5b78841 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -10,6 +10,7 @@ obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o obj-y += clk-tegra-pmc.o obj-y += clk-tegra-fixed.o +obj-y += clk-tegra-osc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o diff --git a/drivers/clk/tegra/clk-tegra-osc.c b/drivers/clk/tegra/clk-tegra-osc.c new file mode 100644 index 0000000..bf8f32c --- /dev/null +++ b/drivers/clk/tegra/clk-tegra-osc.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-id.h" + +#define OSC_CTRL 0x50 +#define OSC_CTRL_OSC_FREQ_SHIFT 28 +#define OSC_CTRL_PLL_REF_DIV_SHIFT 26 + +int __init tegra_osc_clk_init(void __iomem *clk_base, + struct tegra_clk *tegra_clks, + unsigned long *input_freqs, int num, + unsigned long *osc_freq, + unsigned long *pll_ref_freq) +{ + struct clk *clk; + struct clk **dt_clk; + u32 val, pll_ref_div; + unsigned osc_idx; + + val = readl_relaxed(clk_base + OSC_CTRL); + osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT; + + if (osc_idx < num) + *osc_freq = input_freqs[osc_idx]; + + if (!*osc_freq) { + WARN_ON(1); + return -EINVAL; + } + + dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, tegra_clks); + if (!dt_clk) + return 0; + + clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, + *osc_freq); + clk_register_clkdev(clk, "clk_m", NULL); + *dt_clk = clk; + + /* pll_ref */ + val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; + pll_ref_div = 1 << val; + dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, tegra_clks); + if (!dt_clk) + return 0; + + clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", + CLK_SET_RATE_PARENT, 1, pll_ref_div); + clk_register_clkdev(clk, "pll_ref", NULL); + *dt_clk = clk; + + *pll_ref_freq = *osc_freq / pll_ref_div; + + return 0; +} + diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 2598477..b2ddfbf 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -110,10 +110,6 @@ #define PMC_CTRL_BLINK_ENB 7 #define PMC_BLINK_TIMER 0x40 -#define OSC_CTRL 0x50 -#define OSC_CTRL_OSC_FREQ_SHIFT 28 -#define OSC_CTRL_PLL_REF_DIV_SHIFT 26 - #define PLLXC_SW_MAX_P 6 #define CCLKG_BURST_POLICY 0x368 @@ -795,38 +791,6 @@ static struct clk **clks; static unsigned long osc_freq; static unsigned long pll_ref_freq; -static int __init tegra114_osc_clk_init(void __iomem *clk_base) -{ - struct clk *clk; - u32 val, pll_ref_div; - - val = readl_relaxed(clk_base + OSC_CTRL); - - osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT]; - if (!osc_freq) { - WARN_ON(1); - return -EINVAL; - } - - /* clk_m */ - clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, - osc_freq); - clk_register_clkdev(clk, "clk_m", NULL); - clks[TEGRA114_CLK_CLK_M] = clk; - - /* pll_ref */ - val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; - pll_ref_div = 1 << val; - clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", - CLK_SET_RATE_PARENT, 1, pll_ref_div); - clk_register_clkdev(clk, "pll_ref", NULL); - clks[TEGRA114_CLK_PLL_REF] = clk; - - pll_ref_freq = osc_freq / pll_ref_div; - - return 0; -} - static __init void tegra114_utmi_param_configure(void __iomem *clk_base) { u32 reg; @@ -1407,7 +1371,8 @@ static void __init tegra114_clock_init(struct device_node *np) if (!clks) return; - if (tegra114_osc_clk_init(clk_base) < 0) + if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq, + ARRAY_SIZE(tegra114_input_freq), &osc_freq, &pll_ref_freq) < 0) return; tegra_fixed_clk_init(tegra114_clks); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 1f24f2a..3b28178 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -610,6 +610,10 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks); void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks); void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); +int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks, + unsigned long *input_freqs, int num, + unsigned long *osc_freq, + unsigned long *pll_ref_freq); void tegra114_clock_tune_cpu_trimmers_high(void); void tegra114_clock_tune_cpu_trimmers_low(void);