From patchwork Fri Sep 20 21:13:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 2921601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9334EBFF05 for ; Fri, 20 Sep 2013 21:15:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A38EF20459 for ; Fri, 20 Sep 2013 21:15:04 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4DE7720457 for ; Fri, 20 Sep 2013 21:15:03 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VN82G-0007Dw-Su; Fri, 20 Sep 2013 21:14:45 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VN82C-0005v2-3D; Fri, 20 Sep 2013 21:14:40 +0000 Received: from mail-vc0-f202.google.com ([209.85.220.202]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VN820-0005re-LH for linux-arm-kernel@lists.infradead.org; Fri, 20 Sep 2013 21:14:32 +0000 Received: by mail-vc0-f202.google.com with SMTP id gd11so108015vcb.3 for ; Fri, 20 Sep 2013 14:14:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F75zhPjY0vtw7EVKQCk3Asikxv3twiaT34OSC9U9rWI=; b=DIDGNSLqdk85RxEgp/kGZGuHcos8u2e3qCCOVe5Rt/HRoFx2wxeltYgdyM5yOXFKD4 Ez3dVIEWKapclGvsBG2gKT1nwSiX3CgVTp7tRcRPSGV+tBQlR0KkqbdntjYd2jFISbk3 +mY/crVhNUuKxeihIDMHqvrOgoN3w8r+LmffVzWaYsRSTHdepCBjnH2Dytosh7lbHnJe zXR3sL88EEe8BIregA0t8QLJ01X+3NAl8CnIm5q5Avlv1RhYolftN9IX5ybXMRiwQWXQ JPk7fYMs8/b8oBjVJp7+4fVGRNoArq63yWoSY6lQdq2JFhZjad5Fatit8fCr4yflB4C6 IPSw== X-Gm-Message-State: ALoCoQlJDkDRbp9gS5W5x0r2INlvWTCP5V0C6VlDun4cLn1NqlAjdr+R4sojqykNEoNbU2PyyfO8Cegu8bmzdGRtvB4OxY3mrUZrecWNNPO3qBl3eW+87No/KCnJ2j41c+wflA5lQ5g2Ytlg8XpNYeeLfngCxRydiV4Fwp5nflhLr037frx2946qFget+6HGopYq6f+hwyznN8mF6HayG3ncmTdUi5wX5Q== X-Received: by 10.236.142.38 with SMTP id h26mr800987yhj.57.1379711646076; Fri, 20 Sep 2013 14:14:06 -0700 (PDT) Received: from corp2gmr1-2.hot.corp.google.com (corp2gmr1-2.hot.corp.google.com [172.24.189.93]) by gmr-mx.google.com with ESMTPS id t42si1721183yhm.3.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Fri, 20 Sep 2013 14:14:06 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-2.hot.corp.google.com (Postfix) with ESMTP id CE9105A42A8; Fri, 20 Sep 2013 14:14:05 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 8AF6322082B; Fri, 20 Sep 2013 14:14:05 -0700 (PDT) From: Andrew Bresticker To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 2/6] clk: exynos-audss: allow input clocks to be specified in device tree Date: Fri, 20 Sep 2013 14:13:53 -0700 Message-Id: <1379711637-5226-2-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1379711637-5226-1-git-send-email-abrestic@chromium.org> References: <1379711637-5226-1-git-send-email-abrestic@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130920_171428_970923_FAAE26C4 X-CRM114-Status: GOOD ( 16.66 ) X-Spam-Score: 0.2 (/) Cc: Mark Rutland , Yadwinder Singh Brar , linux-doc@vger.kernel.org, Andrew Bresticker , Tomasz Figa , linux-kernel@vger.kernel.org, Tushar Behera , Kukjin Kim , Russell King , Sachin Kamat , Stephen Warren , Grant Likely , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , Rob Herring , Mike Turquette , linux-arm-kernel@lists.infradead.org, Rahul Sharma , Padmavathi Venna , Jiri Kosina , Stephen Boyd , Doug Anderson , Leela Krishna Amudala , Rob Landley X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. Signed-off-by: Andrew Bresticker --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 33 ++++++++++++++++++++-- drivers/clk/samsung/clk-exynos-audss.c | 25 ++++++++++++---- 2 files changed, 51 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 75e2e19..d51a2f9 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -14,6 +14,23 @@ Required Properties: - #clock-cells: should be 1. +Optional Properties: + +- clocks: + - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" + is used if not specified. + - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" + is used if not specified. + - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not + specified. + - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if + not specified. + - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not + specified. + +- clock-names: Aliases for the above clocks. They should be "pll_ref", + "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. Some of the clocks are available only on a particular @@ -35,15 +52,27 @@ sclk_i2s 7 pcm_bus 8 sclk_pcm 9 -Example 1: An example of a clock controller node is listed below. +Example 1: An example of a clock controller node using the default input + clock names is listed below. + +clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; +}; + +Example 2: An example of a clock controller node with audio bus input clock + specified is listed below. clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock 138>; + clock-names = "sclk_audio"; }; -Example 2: I2S controller node that consumes the clock generated by the clock +Example 3: I2S controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 7571e88..aac5342 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -34,10 +34,6 @@ static unsigned long reg_save[][2] = { {ASS_CLK_GATE, 0}, }; -/* list of all parent clock list */ -static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; -static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; - #ifdef CONFIG_PM_SLEEP static int exynos_audss_clk_suspend(void) { @@ -66,6 +62,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = { /* register exynos_audss clocks */ static int exynos_audss_clk_probe(struct platform_device *pdev) { + const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; + const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; + const char *sclk_pcm_p = "sclk_pcm0"; + struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; struct resource *res; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -88,11 +88,23 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, &clk_data); + pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); + pll_in = devm_clk_get(&pdev->dev, "pll_in"); + if (!IS_ERR(pll_ref)) + mout_audss_p[0] = __clk_get_name(pll_ref); + if (!IS_ERR(pll_in)) + mout_audss_p[1] = __clk_get_name(pll_in); clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); + cdclk = devm_clk_get(&pdev->dev, "cdclk"); + sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); + if (!IS_ERR(cdclk)) + mout_i2s_p[1] = __clk_get_name(cdclk); + if (!IS_ERR(sclk_audio)) + mout_i2s_p[2] = __clk_get_name(sclk_audio); clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, @@ -126,8 +138,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); + sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); + if (!IS_ERR(sclk_pcm_in)) + sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", - "div_pcm0", CLK_SET_RATE_PARENT, + sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); #ifdef CONFIG_PM_SLEEP