| Message ID | 1379711637-5226-3-git-send-email-abrestic@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Andrew, On Friday 20 of September 2013 14:13:54 Andrew Bresticker wrote: > There is no gate for the PCM clock input to the AudioSS block, so > the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that > we can reference it in device trees. > > Signed-off-by: Andrew Bresticker <abrestic@chromium.org> > --- > Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 + > drivers/clk/samsung/clk-exynos5250.c | 4 ++-- > 2 files changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Tomasz Figa <t.figa@samsung.com> Best regards, Tomasz
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 24765c1..67e9a47 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -62,6 +62,7 @@ clock which they consume. div_i2s1 157 div_i2s2 158 sclk_hdmiphy 159 + div_pcm0 160 [Peripheral Clock Gates] diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index adf3234..dec5376 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -108,7 +108,7 @@ enum exynos5250_clks { sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3, sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm, sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, - div_i2s1, div_i2s2, sclk_hdmiphy, + div_i2s1, div_i2s2, sclk_hdmiphy, div_pcm0, /* gate clocks */ gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0, @@ -301,7 +301,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), - DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), + DIV(div_pcm0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> --- Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 + drivers/clk/samsung/clk-exynos5250.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-)