From patchwork Tue Sep 24 18:06:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 2934931 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 61091BFF05 for ; Tue, 24 Sep 2013 18:07:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9902B203E5 for ; Tue, 24 Sep 2013 18:07:38 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C1DB7202F8 for ; Tue, 24 Sep 2013 18:07:33 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOX1E-000390-Iz; Tue, 24 Sep 2013 18:07:28 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOX1C-0008PS-Cc; Tue, 24 Sep 2013 18:07:26 +0000 Received: from mail-qe0-f73.google.com ([209.85.128.73]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOX17-0008Mj-B1 for linux-arm-kernel@lists.infradead.org; Tue, 24 Sep 2013 18:07:22 +0000 Received: by mail-qe0-f73.google.com with SMTP id 6so566542qea.2 for ; Tue, 24 Sep 2013 11:07:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=19MmNjoGUtwpqm0VBwBGBRgUX9jo9XT+zG9AQc5/a4A=; b=iKrXSjoCdXVBaMIl2oP+rmrFuLDCpfaP0WXO7Ep5ezf0ujeOPbhSQjyNa7pKc8fpVT 5xP3DL3CF0jY7MyPvkuZoi/2nRDU87gd3mNLkr+1/g1TVxYBS3Zyfv6KK4lZV3ozUeLX auaHVDr3PDAlrnSHIySqU7vSYRWrkhjCjbYizEKKNhutZsOgyUUJDEscMK+NUCtyvcCe SwrHm5xswNAlHooJcMR//QzVG+96J4em0Qwk6qEIGWRw8GcWjfiPVtqkafzAEapC/LiH C7XS8AlX5w8FRGxjEKl5n3htL2BfSkYRbp9Mm3XPitgWru5nPbpTxlEFfCoqFbz4eCnV aYIg== X-Gm-Message-State: ALoCoQl4PSRScwOzVcOOUj53z1ThGmOYpZyT/EPuUV7BxFPxAHHiUhvho5tVo6vqlj9bJ228s9HDMrefO7Rwh00e2dZYMTvZNVB6fx+EOGqWr40eau1/ZcgLDwLKvdhmuxcpBRBPzU63mQLzSK00HrjGFaPHbd4ORElfs40FL8x+RKS0IgIujFd14Y/odW5KdpTKGdThNtdSdjXNEy5F+Q+lSuU9f4+xdA== X-Received: by 10.236.174.232 with SMTP id x68mr8819140yhl.42.1380046020583; Tue, 24 Sep 2013 11:07:00 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id z45si4561399yha.7.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Tue, 24 Sep 2013 11:07:00 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 2CB5B31C1BD; Tue, 24 Sep 2013 11:07:00 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id D8BDE220A39; Tue, 24 Sep 2013 11:06:59 -0700 (PDT) From: Andrew Bresticker To: linux-samsung-soc@vger.kernel.org, Tomasz Figa , Sylwester Nawrocki Subject: [PATCH V3 2/6] clk: exynos-audss: allow input clocks to be specified in device tree Date: Tue, 24 Sep 2013 11:06:52 -0700 Message-Id: <1380046016-5811-2-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1380046016-5811-1-git-send-email-abrestic@chromium.org> References: <1379982078-23381-1-git-send-email-abrestic@chromium.org> <1380046016-5811-1-git-send-email-abrestic@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130924_140721_493381_A3E08E4F X-CRM114-Status: GOOD ( 16.32 ) X-Spam-Score: -1.5 (-) Cc: Mark Rutland , linux-doc@vger.kernel.org, Andrew Bresticker , linux-kernel@vger.kernel.org, Tushar Behera , Kukjin Kim , Russell King , Sachin Kamat , Stephen Warren , Grant Likely , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , Rob Herring , Mike Turquette , linux-arm-kernel@lists.infradead.org, Rahul Sharma , Padmavathi Venna , Jiri Kosina , Stephen Boyd , Doug Anderson , Leela Krishna Amudala , Rob Landley X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. Signed-off-by: Andrew Bresticker --- Changes since v1: - listed input clocks as required properties --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 32 ++++++++++++++++++++-- drivers/clk/samsung/clk-exynos-audss.c | 25 +++++++++++++---- 2 files changed, 50 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 75e2e19..85b9e28 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -14,6 +14,21 @@ Required Properties: - #clock-cells: should be 1. +- clocks: + - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" + is used if not specified. + - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" + is used if not specified. + - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not + specified. + - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if + not specified. + - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not + specified. + +- clock-names: Aliases for the above clocks. They should be "pll_ref", + "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. Some of the clocks are available only on a particular @@ -35,15 +50,28 @@ sclk_i2s 7 pcm_bus 8 sclk_pcm 9 -Example 1: An example of a clock controller node is listed below. +Example 1: An example of a clock controller node using the default input + clock names is listed below. + +clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; +}; + +Example 2: An example of a clock controller node with the input clocks + specified. clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, + <&ext_i2s_clk>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk"; }; -Example 2: I2S controller node that consumes the clock generated by the clock +Example 3: I2S controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 319c6e4..e7e800a 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -34,10 +34,6 @@ static unsigned long reg_save[][2] = { {ASS_CLK_GATE, 0}, }; -/* list of all parent clock list */ -static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; -static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; - #ifdef CONFIG_PM_SLEEP static int exynos_audss_clk_suspend(void) { @@ -68,6 +64,10 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) { int i, ret = 0; struct resource *res; + const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; + const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; + const char *sclk_pcm_p = "sclk_pcm0"; + struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg_base = devm_ioremap_resource(&pdev->dev, res); @@ -82,11 +82,23 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) if (!clk_table) return -ENOMEM; + pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); + pll_in = devm_clk_get(&pdev->dev, "pll_in"); + if (!IS_ERR(pll_ref)) + mout_audss_p[0] = __clk_get_name(pll_ref); + if (!IS_ERR(pll_in)) + mout_audss_p[1] = __clk_get_name(pll_in); clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); + cdclk = devm_clk_get(&pdev->dev, "cdclk"); + sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); + if (!IS_ERR(cdclk)) + mout_i2s_p[1] = __clk_get_name(cdclk); + if (!IS_ERR(sclk_audio)) + mout_i2s_p[2] = __clk_get_name(sclk_audio); clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, @@ -120,8 +132,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); + sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); + if (!IS_ERR(sclk_pcm_in)) + sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", - "div_pcm0", CLK_SET_RATE_PARENT, + sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); for (i = 0; i < EXYNOS_AUDSS_MAX_CLKS; i++) {