From patchwork Tue Sep 24 21:11:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2935811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AFD62BFF05 for ; Tue, 24 Sep 2013 21:13:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7D1BF202DD for ; Tue, 24 Sep 2013 21:13:18 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0AFB72041B for ; Tue, 24 Sep 2013 21:13:15 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOZuY-0006Ux-PF; Tue, 24 Sep 2013 21:12:46 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOZuO-00050U-5l; Tue, 24 Sep 2013 21:12:36 +0000 Received: from co9ehsobe004.messaging.microsoft.com ([207.46.163.27] helo=co9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOZuF-0004yY-6z for linux-arm-kernel@lists.infradead.org; Tue, 24 Sep 2013 21:12:29 +0000 Received: from mail181-co9-R.bigfish.com (10.236.132.238) by CO9EHSOBE013.bigfish.com (10.236.130.76) with Microsoft SMTP Server id 14.1.225.22; Tue, 24 Sep 2013 21:12:05 +0000 Received: from mail181-co9 (localhost [127.0.0.1]) by mail181-co9-R.bigfish.com (Postfix) with ESMTP id 92D915C0151; Tue, 24 Sep 2013 21:12:05 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz8275ch1de098h1de097h8275bh8275dhz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1fe8h1ff5h1155h) Received-SPF: pass (mail181-co9: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail181-co9 (localhost.localdomain [127.0.0.1]) by mail181-co9 (MessageSwitch) id 1380057123581275_23923; Tue, 24 Sep 2013 21:12:03 +0000 (UTC) Received: from CO9EHSMHS021.bigfish.com (unknown [10.236.132.247]) by mail181-co9.bigfish.com (Postfix) with ESMTP id 7DE19C8006F; Tue, 24 Sep 2013 21:12:03 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by CO9EHSMHS021.bigfish.com (10.236.130.31) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 24 Sep 2013 21:12:03 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Tue, 24 Sep 2013 14:00:52 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.71]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r8OLC0xp028963; Tue, 24 Sep 2013 14:12:01 -0700 (PDT) From: To: Subject: [PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform Date: Tue, 24 Sep 2013 16:11:59 -0500 Message-ID: <1380057120-27108-1-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130924_171227_463624_82E03CAD X-CRM114-Status: GOOD ( 13.34 ) X-Spam-Score: -0.8 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Arnd Bergmann , Pawel Moll , Stephen Warren , Pavel Machek , Rob Herring , linux-arm-kernel@lists.infradead.org, Olof Johansson , Dinh Nguyen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The STMMAC Ethernet controller in SOCFPGA requires setting a register for the phy-mode that is outside of the ethernet IP. This register resides in the System Manager block. So we define a new DTS binding "altr,sysmgr-phy-mask". This binding's property is a bitmask that can be used to set the correct register bit. Signed-off-by: Dinh Nguyen Cc: Pavel Machek CC: Arnd Bergmann CC: Olof Johansson Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- .../bindings/net/stmmac-altr-socfpga.txt | 43 ++++++++++++++++++++ arch/arm/boot/dts/socfpga_cyclone5.dts | 19 +++++++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt new file mode 100644 index 0000000..f0fa56a --- /dev/null +++ b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt @@ -0,0 +1,43 @@ +* Altera SOCFPGA specific extensions to the STMicroelectronics + 10/100/1000 Ethernet driver (GMAC) + +This file documents an additional property that is required for the Altera +SOCFPGA implementation of the STMMAC Ethernet driver. Please refer to the core +properties of the STMMAC driver as documented in stmmac.txt. + +Required Properties: + +* compatible: should be + - "altr,socfpga-stmmac": for controllers with Altera SOCFPGA specific + extensions. + +* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to + set the appropriate register bits for the phy-mode in the System Manager. + The value should be: + -Ethernet Controller 1 (gmac0) = 0x3 + -Ethernet Controller 2 (gmac1) = 0xC + +Example: + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq""; + mac-address = [000000000000]; /* Filled in by U-Boot */ + phy-mode = "gmii"; + + /* PHY Skew settings */ + rxd0-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; + + altr,sysmgr-phy-mask = <0x3>; + status = "okay"; + }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index bfed066..44db0e6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -95,3 +95,22 @@ }; }; }; + +&gmac1 { + phy-mode = "rgmii"; + snps,phy-addr = <0xffffffff>; /* probe for phy addr */ + + rxd0-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; + + altr,sysmgr-phy-mask = <0xC>; + status = "okay"; +}; +