From patchwork Tue Sep 24 21:12:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2935821 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3531A9F288 for ; Tue, 24 Sep 2013 21:13:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0BECB202E5 for ; Tue, 24 Sep 2013 21:13:26 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2327202DD for ; Tue, 24 Sep 2013 21:13:24 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOZue-0006bY-Ui; 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envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail56-co9 (localhost.localdomain [127.0.0.1]) by mail56-co9 (MessageSwitch) id 1380057126180445_21577; Tue, 24 Sep 2013 21:12:06 +0000 (UTC) Received: from CO9EHSMHS023.bigfish.com (unknown [10.236.132.226]) by mail56-co9.bigfish.com (Postfix) with ESMTP id 1C655500051; Tue, 24 Sep 2013 21:12:06 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by CO9EHSMHS023.bigfish.com (10.236.130.33) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 24 Sep 2013 21:12:04 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Tue, 24 Sep 2013 14:00:53 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.71]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r8OLC0xq028963; Tue, 24 Sep 2013 14:12:02 -0700 (PDT) From: To: Subject: [PATCH 2/2] arm: socfpga: Add platform initialization for ethernet Date: Tue, 24 Sep 2013 16:12:00 -0500 Message-ID: <1380057120-27108-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1380057120-27108-1-git-send-email-dinguyen@altera.com> References: <1380057120-27108-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130924_171229_522197_E14F9853 X-CRM114-Status: GOOD ( 19.28 ) X-Spam-Score: -0.8 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Arnd Bergmann , Pawel Moll , Stephen Warren , Pavel Machek , Rob Herring , linux-arm-kernel@lists.infradead.org, Olof Johansson , Dinh Nguyen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen In order to correctly enable ethernet support on SOCFGPA, a couple of platform specific initializations steps must be done. 1) Use the phy-mode DTS property to set the appropriate bits in a system manager register. 2) The ethernet IP should only be brought out of reset when initialized. Signed-off-by: Dinh Nguyen Cc: Pavel Machek CC: Arnd Bergmann CC: Olof Johansson Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- arch/arm/mach-socfpga/core.h | 9 +++++ arch/arm/mach-socfpga/socfpga.c | 72 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 80 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index b05fa6a..474582b 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -28,6 +28,15 @@ #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ +/* Peripheral Module Reset Register bits */ +#define RSTMGR_PERMODRST_EMAC0 0x1 +#define RSTMGR_PERMODRST_EMAC1 0x2 + +#define SYSMGR_EMACGRP_CTRL_OFFSET 0x60 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + extern void socfpga_secondary_startup(void); extern void __iomem *socfpga_scu_base_addr; diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index bfce964..fe97423 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -19,7 +19,10 @@ #include #include #include +#include +#include #include +#include #include #include @@ -33,6 +36,24 @@ void __iomem *rst_manager_base_addr; void __iomem *clk_mgr_base_addr; unsigned long cpu1start_addr; +static int stmmac_plat_init(struct platform_device *pdev); + +static struct plat_stmmacenet_data stmmacenet0_data = { + .init = &stmmac_plat_init, + .bus_id = 0, +}; + +static struct plat_stmmacenet_data stmmacenet1_data = { + .init = &stmmac_plat_init, + .bus_id = 1, +}; + +static const struct of_dev_auxdata socfpga_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff700000, NULL, &stmmacenet0_data), + OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff702000, NULL, &stmmacenet1_data), + { /* sentinel */ } +}; + static struct map_desc scu_io_desc __initdata = { .virtual = SOCFPGA_SCU_VIRT_BASE, .pfn = 0, /* run-time */ @@ -47,6 +68,54 @@ static struct map_desc uart_io_desc __initdata = { .type = MT_DEVICE, }; +static int stmmac_plat_init(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + u32 ctrl, val; + u32 rstmask, sysmgr_phymask; + int phymode; + + if (of_machine_is_compatible("altr,socfpga-vt")) + return 0; + + phymode = of_get_phy_mode(np); + if (of_property_read_u32(np, "altr,sysmgr-phy-mask", &sysmgr_phymask)) + pr_err("GMAC: No altr,sysmgr-phy-mask property found!\n"); + + switch (phymode) { + case PHY_INTERFACE_MODE_RGMII: + val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + break; + default: + pr_err("%s bad phy mode %d", __func__, phymode); + return -EINVAL; + } + + if (sysmgr_phymask == 0xC) { + /* gmac1 */ + val |= (val << 2); + rstmask = RSTMGR_PERMODRST_EMAC1; + } else + rstmask = RSTMGR_PERMODRST_EMAC0; + + /* Set the PHY mode in the system manager.*/ + ctrl = readl(sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET); + ctrl &= ~sysmgr_phymask; + ctrl |= val; + writel(ctrl, (sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET)); + + /* Bring the appropriate ethernet ip out of reset.*/ + ctrl = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST); + ctrl &= ~rstmask; + writel(ctrl, rst_manager_base_addr + SOCFPGA_RSTMGR_MODPERRST); + + return 0; +} + static void __init socfpga_scu_map_io(void) { unsigned long base; @@ -106,7 +175,8 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) static void __init socfpga_cyclone5_init(void) { l2x0_of_init(0, ~0UL); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, + socfpga_auxdata_lookup, NULL); of_clk_init(NULL); socfpga_init_clocks(); }