From patchwork Thu Sep 26 03:33:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 2946501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3AB679F3C4 for ; Thu, 26 Sep 2013 03:34:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5A3DA20334 for ; Thu, 26 Sep 2013 03:34:21 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 54EC82032D for ; Thu, 26 Sep 2013 03:34:20 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VP2KW-0007YO-Uf; Thu, 26 Sep 2013 03:33:29 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VP2KG-0000Ln-O1; Thu, 26 Sep 2013 03:33:12 +0000 Received: from mail-db8lp0187.outbound.messaging.microsoft.com ([213.199.154.187] helo=db8outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VP2K5-0000Js-Ok for linux-arm-kernel@lists.infradead.org; Thu, 26 Sep 2013 03:33:03 +0000 Received: from mail159-db8-R.bigfish.com (10.174.8.240) by DB8EHSOBE013.bigfish.com (10.174.4.76) with Microsoft SMTP Server id 14.1.225.22; Thu, 26 Sep 2013 03:32:41 +0000 Received: from mail159-db8 (localhost [127.0.0.1]) by mail159-db8-R.bigfish.com (Postfix) with ESMTP id 6FF5E3600C6; Thu, 26 Sep 2013 03:32:40 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bh8275dhz2dh87h2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1151h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail159-db8 (localhost.localdomain [127.0.0.1]) by mail159-db8 (MessageSwitch) id 1380166317525213_13450; Thu, 26 Sep 2013 03:31:57 +0000 (UTC) Received: from DB8EHSMHS028.bigfish.com (unknown [10.174.8.233]) by mail159-db8.bigfish.com (Postfix) with ESMTP id 71371440165; Thu, 26 Sep 2013 03:31:57 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS028.bigfish.com (10.174.4.38) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 26 Sep 2013 03:31:54 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 26 Sep 2013 03:31:53 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.193]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r8Q3Vk7m008163; Wed, 25 Sep 2013 20:31:50 -0700 From: Shawn Guo To: Subject: [PATCH 1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q Date: Thu, 26 Sep 2013 11:33:30 +0800 Message-ID: <1380166412-13586-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1380166412-13586-1-git-send-email-shawn.guo@linaro.org> References: <1380166412-13586-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130925_233302_059455_7EEF925B X-CRM114-Status: GOOD ( 12.80 ) X-Spam-Score: -1.9 (-) Cc: Zhu Richard-R65037 , tharvey@gateworks.com, Frank Li , Sean Cross , Shawn Guo , Sascha Hauer X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sean Cross The i.MX6 has two general-purpose LVDS clocks that can be driven from a variety of sources. This patch adds a mux and a gate for both of these clocks. Signed-off-by: Sean Cross Signed-off-by: Shawn Guo --- .../devicetree/bindings/clock/imx6q-clock.txt | 4 ++++ arch/arm/mach-imx/clk-imx6q.c | 20 +++++++++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index e8b1baa..6aab72b 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -216,6 +216,10 @@ clocks and IDs. cko 201 vdoa 202 pll4_audio_div 203 + lvds1_sel 204 + lvds2_sel 205 + lvds1_gate 206 + lvds2_gate 207 Examples: diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 913ad85..0e7f3bc 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -217,6 +217,11 @@ static const char *cko2_sels[] = { "uart_serial", "spdif", "asrc", "hsi_tx", }; static const char *cko_sels[] = { "cko1", "cko2", }; +static const char *lvds_sels[] = { + "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", + "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", + "pcie_ref", "sata_ref", +}; enum mx6q_clks { dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, @@ -251,7 +256,8 @@ enum mx6q_clks { ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, - spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, clk_max + spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, + lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max }; static struct clk *clk[clk_max]; @@ -342,6 +348,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); + clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); + clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); + + /* + * lvds1_gate and lvds2_gate are pseudo-gates. Both can be + * independently configured as clock inputs or outputs. We treat + * the "output_enable" bit as a gate, even though it's really just + * enabling clock output. + */ + clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); + clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); + /* name parent_name reg idx */ clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);