From patchwork Thu Sep 26 19:01:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 2950921 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4B4D2BFF0B for ; Thu, 26 Sep 2013 19:05:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0AA89202EB for ; Thu, 26 Sep 2013 19:05:04 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B400202E6 for ; Thu, 26 Sep 2013 19:05:02 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VPGqc-0001Uu-Mr; Thu, 26 Sep 2013 19:03:35 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VPGq9-0000Fg-7A; Thu, 26 Sep 2013 19:03:05 +0000 Received: from mail-pd0-f180.google.com ([209.85.192.180]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VPGpI-00006M-IF for linux-arm-kernel@lists.infradead.org; Thu, 26 Sep 2013 19:02:17 +0000 Received: by mail-pd0-f180.google.com with SMTP id y10so1541857pdj.39 for ; Thu, 26 Sep 2013 12:01:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y4J1lvZxFhhx0wamBI8WzDr8QmtLN/nd3rwwSO5ejmQ=; b=V/X+TMBiCJqCIfDgqvE6W5DfbxgK3qtRgiiH1EzM6xZXTjmI/C8kGfHJs/zVwQ74ji ROxg6mgHJpSY/wwWSzTjPnjo4OVC4FunDE7Vl/WFI1X3cBUinqL/V2IadGjvfkJhoZve aFuoyAtyTKkAvMVj0vj2qVsR79iOfOgDmYbRUZj7zL1foUY9Sj54c9y7jnhRoLq66rOm Wfnm9DHQisknpetHgKVhk5aTe5pHD3/sfT+X6WhzyIcnAtU9PRxPeJlOe5iN0vQ7E4JC OoGpydQ+UwqlgCFBtIYlHbMznNhzv8495eaQWssiTIDLS+zqhGTJZhMNamxxOsJyxGYy tXxQ== X-Gm-Message-State: ALoCoQnO2EpMpGf3EJtDcJgteupQc3GTr3SkHrTtdcOhSZnAfxU6plbWosrTJL3BuQdBT1F3r8Cm X-Received: by 10.66.248.161 with SMTP id yn1mr7386935pac.0.1380222111112; Thu, 26 Sep 2013 12:01:51 -0700 (PDT) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id k4sm3870767pbd.11.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 12:01:50 -0700 (PDT) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu Subject: [PATCH v2 7/8] KVM: arm-vgic: Add GICD_SPENDSGIR and GICD_CPENDSGIR handlers Date: Thu, 26 Sep 2013 12:01:36 -0700 Message-Id: <1380222097-20251-8-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1380222097-20251-1-git-send-email-christoffer.dall@linaro.org> References: <1380222097-20251-1-git-send-email-christoffer.dall@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130926_150212_770731_E3CF91DB X-CRM114-Status: GOOD ( 13.91 ) X-Spam-Score: 0.6 (/) Cc: Christoffer Dall , linaro-kernel@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, SUSPICIOUS_RECIPS, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Handle MMIO accesses to the two registers which should support both the case where the VMs want to read/write either of these registers and the case where user space reads/writes these registers to do save/restore of the VGIC state. Note that the added complexity compared to simple set/clear enable registers stems from the bookkeping of source cpu ids. It may be possible to change the underlying data structure to simplify the complexity, but since this is not in the critical path, at all, this is left as an interesting excercise to the reader. Signed-off-by: Christoffer Dall Reviewed-by: Alexander Graf --- Changelog[v2]: - Use struct kvm_exit_mmio accessors for ->data field. --- virt/kvm/arm/vgic.c | 114 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 112 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index f2dc72a..4e8c3ab 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -589,18 +589,128 @@ static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu, return false; } +static void read_sgi_set_clear(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + int i, sgi, cpu; + int min_sgi = (offset & ~0x3) * 4; + int max_sgi = min_sgi + 3; + int vcpu_id = vcpu->vcpu_id; + u32 lr, reg = 0; + + /* Copy source SGIs from distributor side */ + for (sgi = min_sgi; sgi <= max_sgi; sgi++) { + int shift = 8 * (sgi - min_sgi); + reg |= (u32)dist->irq_sgi_sources[vcpu_id][sgi] << shift; + } + + /* Copy source SGIs already on LRs */ + for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { + lr = vgic_cpu->vgic_lr[i]; + sgi = lr & GICH_LR_VIRTUALID; + cpu = (lr & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT; + if (sgi >= min_sgi && sgi <= max_sgi) { + if (lr & GICH_LR_STATE) + reg |= (1 << cpu) << (8 * (sgi - min_sgi)); + } + } + + mmio_data_write(mmio, ~0, reg); +} + static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { - return false; + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + int i, sgi, cpu; + int min_sgi = (offset & ~0x3) * 4; + int max_sgi = min_sgi + 3; + int vcpu_id = vcpu->vcpu_id; + u32 *lr, reg; + bool updated = false; + + if (!mmio->is_write) { + read_sgi_set_clear(vcpu, mmio, offset); + return false; + } + + reg = mmio_data_read(mmio, ~0); + + /* Clear pending SGIs on distributor side */ + for (sgi = min_sgi; sgi <= max_sgi; sgi++) { + u8 mask = reg >> (8 * (sgi - min_sgi)); + if (dist->irq_sgi_sources[vcpu_id][sgi] & mask) + updated = true; + dist->irq_sgi_sources[vcpu_id][sgi] &= ~mask; + } + + /* Clear SGIs already on LRs */ + for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { + lr = &vgic_cpu->vgic_lr[i]; + sgi = *lr & GICH_LR_VIRTUALID; + cpu = (*lr & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT; + + if (sgi >= min_sgi && sgi <= max_sgi) { + if (reg & ((1 << cpu) << (8 * (sgi - min_sgi)))) { + if (*lr & GICH_LR_PENDING_BIT) + updated = true; + *lr &= GICH_LR_PENDING_BIT; + } + } + } + + return updated; } static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { - return false; + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + int i, sgi, cpu; + int min_sgi = (offset & ~0x3) * 4; + int max_sgi = min_sgi + 3; + int vcpu_id = vcpu->vcpu_id; + u32 *lr, reg; + bool updated = false; + + if (!mmio->is_write) { + read_sgi_set_clear(vcpu, mmio, offset); + return false; + } + + reg = mmio_data_read(mmio, ~0); + + /* Set pending SGIs on distributor side */ + for (sgi = min_sgi; sgi <= max_sgi; sgi++) { + u8 mask = reg >> (8 * (sgi - min_sgi)); + if ((dist->irq_sgi_sources[vcpu_id][sgi] & mask) != mask) + updated = true; + dist->irq_sgi_sources[vcpu_id][sgi] |= mask; + } + + /* Set active SGIs already on LRs to pending and active */ + for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { + lr = &vgic_cpu->vgic_lr[i]; + sgi = *lr & GICH_LR_VIRTUALID; + cpu = (*lr & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT; + + if (sgi >= min_sgi && sgi <= max_sgi) { + if (reg & ((1 << cpu) << (8 * (sgi - min_sgi)))) { + if (!(*lr & GICH_LR_PENDING_BIT)) + updated = true; + *lr |= GICH_LR_PENDING_BIT; + } + } + } + + return updated; } /*