From patchwork Thu Sep 26 19:35:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 2951161 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E10269F288 for ; Thu, 26 Sep 2013 19:37:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D0BBE202C1 for ; Thu, 26 Sep 2013 19:37:08 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D388B201FF for ; Thu, 26 Sep 2013 19:37:07 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VPHMX-0000Is-IO; Thu, 26 Sep 2013 19:36:33 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VPHMN-0001It-Ph; Thu, 26 Sep 2013 19:36:23 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VPHM2-0001G2-Oy for linux-arm-kernel@lists.infradead.org; Thu, 26 Sep 2013 19:36:04 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 0769289F; Thu, 26 Sep 2013 21:35:45 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (unknown [190.2.109.158]) by mail.free-electrons.com (Postfix) with ESMTPA id DD180618; Thu, 26 Sep 2013 21:35:41 +0200 (CEST) From: Ezequiel Garcia To: Subject: [PATCH v2 2/4] ARM: mvebu: Add Core Divider clock device-tree binding Date: Thu, 26 Sep 2013 16:35:28 -0300 Message-Id: <1380224130-11868-3-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1380224130-11868-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1380224130-11868-1-git-send-email-ezequiel.garcia@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130926_153602_955001_588B7CA9 X-CRM114-Status: UNSURE ( 7.85 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -3.7 (---) Cc: Lior Amsalem , Andrew Lunn , Mike Turquette , Jason Cooper , Tawfik Bayouk , Ezequiel Garcia , Gregory Clement , Thomas Petazzoni , Emilio Lopez X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Armada 370/XP SoCs have a Core Divider clock providing several clocks. For now, only the NAND clock is supported. Reviewed-by: Gregory CLEMENT Signed-off-by: Ezequiel Garcia --- .../devicetree/bindings/clock/mvebu-corediv-clock.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt new file mode 100644 index 0000000..c62391f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt @@ -0,0 +1,19 @@ +* Core Divider Clock bindings for Marvell MVEBU SoCs + +The following is a list of provided IDs and clock names on Armada 370/XP: + 0 = nand (NAND clock) + +Required properties: +- compatible : must be "marvell,armada-370-corediv-clock" +- reg : must be the register address of Core Divider control register +- #clock-cells : from common clock binding; shall be set to 1 +- clocks : must be set to the parent's phandle + +Example: + +corediv_clk: corediv-clocks@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&pll>; +};