From patchwork Wed Oct 2 12:34:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerlando Falauto X-Patchwork-Id: 2974581 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C9158BFF0B for ; Wed, 2 Oct 2013 12:35:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 085F3203DD for ; Wed, 2 Oct 2013 12:35:03 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E324E2038B for ; Wed, 2 Oct 2013 12:34:57 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VRLdl-0002sG-H1; Wed, 02 Oct 2013 12:34:53 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VRLdj-00077S-8A; Wed, 02 Oct 2013 12:34:51 +0000 Received: from mail-de.keymile.com ([195.8.104.250]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VRLdf-00076q-L0 for linux-arm-kernel@lists.infradead.org; Wed, 02 Oct 2013 12:34:48 +0000 Received: from [10.9.1.54] (port=54533 helo=mailrelay.de.keymile.net) by mail-de.keymile.com with esmtp (Exim 4.76) (envelope-from ) id 1VRLdI-00079i-00; Wed, 02 Oct 2013 14:34:24 +0200 Received: from chber1-10555x.ch.keymile.net ([172.31.40.82]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id r92CVw1W000072; Wed, 2 Oct 2013 14:31:58 +0200 (MEST) From: Gerlando Falauto To: linux@vger.kernel.org Subject: [PATCH 1/1] gpio: mvebu: enable and use IRQ_GC_MASK_CACHE_PER_TYPE Date: Wed, 2 Oct 2013 14:34:19 +0200 Message-Id: <1380717259-11060-1-git-send-email-gerlando.falauto@keymile.com> X-Mailer: git-send-email 1.8.0.1 In-Reply-To: <1380717118-10860-1-git-send-email-gerlando.falauto@keymile.com> References: <1380717118-10860-1-git-send-email-gerlando.falauto@keymile.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131002_083447_921266_A4EEE45D X-CRM114-Status: GOOD ( 10.35 ) X-Spam-Score: 0.8 (/) Cc: Thomas Petazzoni , Andrew Lunn , Linus Walleij , Arnd Bergmann , Linus Walleij , Grant Likely , Simon Guinot , Gerlando Falauto , Gregory Clement , Sebastian Hesselbarth , linux-arm-kernel@lists.infradead.org, Jason Cooper X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since we have now introduced mask_cache within irq_chip_type to also handle per-chip-type mask registers, convert gpio-mvebu driver to use this new pointer. Also enable IRQ_GC_MASK_CACHE_PER_TYPE to actually handle separate mask registers for all three SoC variants handled by this driver. This wll fix a bug where requesting (and triggering) both EDGE- and LEVEL- based IRQs causes the kernel to hang. Signed-off-by: Gerlando Falauto Cc: Simon Guinot Cc: Thomas Petazzoni Cc: Grant Likely Cc: Linus Walleij Cc: Andrew Lunn Cc: Jason Cooper Cc: Gregory Clement Cc: Sebastian Hesselbarth Cc: Linus Walleij Cc: Andrew Lunn Cc: Arnd Bergmann Cc: linux-arm-kernel@lists.infradead.org --- drivers/gpio/gpio-mvebu.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c index 3a4816a..ce425b3 100644 --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c @@ -303,48 +303,52 @@ static void mvebu_gpio_irq_ack(struct irq_data *d) static void mvebu_gpio_edge_irq_mask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache &= ~mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); + *ct->mask_cache &= ~mask; + writel_relaxed(*ct->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache |= mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); + *ct->mask_cache |= mask; + writel_relaxed(*ct->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_level_irq_mask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache &= ~mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); + *ct->mask_cache &= ~mask; + writel_relaxed(*ct->mask_cache, mvebu_gpioreg_level_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_level_irq_unmask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache |= mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); + *ct->mask_cache |= mask; + writel_relaxed(*ct->mask_cache, mvebu_gpioreg_level_mask(mvchip)); irq_gc_unlock(gc); } @@ -708,7 +712,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev) ct->handler = handle_edge_irq; ct->chip.name = mvchip->chip.label; - irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0, + irq_setup_generic_chip(gc, IRQ_MSK(ngpios), + IRQ_GC_MASK_CACHE_PER_TYPE, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); /* Setup irq domain on top of the generic chip. */