From patchwork Tue Oct 8 14:36:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soren Brinkmann X-Patchwork-Id: 3003981 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 69C2ABF924 for ; Tue, 8 Oct 2013 14:37:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B1E9A201BE for ; Tue, 8 Oct 2013 14:37:13 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E0F402016A for ; Tue, 8 Oct 2013 14:37:08 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTYPJ-000160-82; Tue, 08 Oct 2013 14:37:05 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTYPG-0001UG-Ld; Tue, 08 Oct 2013 14:37:02 +0000 Received: from mail-pb0-x22f.google.com ([2607:f8b0:400e:c01::22f]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTYPD-0001SZ-5S for linux-arm-kernel@lists.infradead.org; Tue, 08 Oct 2013 14:37:00 +0000 Received: by mail-pb0-f47.google.com with SMTP id rr4so8677973pbb.6 for ; Tue, 08 Oct 2013 07:36:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=k82iFwOzZEqVBpVXwhzqqPqq94Mg7njizLcd6fpf4EY=; b=ItpnLzyFGYsfQJ+CnWUadnrjQfV4N0YuZawtDatSZe4DNhksrPVlJyzQyAQ+maVv3F 84bgIwxtOoItZ9GFGTjrqq60VK4W8XUTqdhwKk/rdF68VcFhW4160VsgSVNEC24I7tNg tvlwJpQFUowGZ4UXQBtTCd5C9o5H68/gy2Nh78n+Xz8BvQ7r28UsE9xWF3Wu/WZRX+/i ic3ZHPiLA6o64ZUzyUErzELm7gFO/RvvH00lJ71j2fFkkFYzIpLlVnfPDUBySUm8u2wl pzuUUrYUxbe8Tjk31xcHDPymHK5w9VQY+48REOy0NVzMXCzDHMbGwCqv9WPSAR+MPH80 G6/Q== X-Received: by 10.66.231.42 with SMTP id td10mr3950919pac.144.1381242995352; Tue, 08 Oct 2013 07:36:35 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id ry4sm47854878pab.4.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 08 Oct 2013 07:36:33 -0700 (PDT) From: Soren Brinkmann To: Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Mike Turquette , Michal Simek Subject: [PATCH 1/2] clk/zynq/clkc: Add 'fclk-enable' feature Date: Tue, 8 Oct 2013 07:36:11 -0700 Message-Id: <1381242972-14752-1-git-send-email-soren.brinkmann@xilinx.com> X-Mailer: git-send-email 1.8.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131008_103659_333173_937F750B X-CRM114-Status: GOOD ( 16.40 ) X-Spam-Score: -1.9 (-) Cc: Soren Brinkmann , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In some use cases Zynq's FPGA clocks are used as static clock generators for IP in the FPGA part of the SOC for which no Linux driver exists and would control those clocks. To avoid automatic gating of these clocks in such cases a new property - fclk-enable - is added to the clock controller's DT description to accomodate such use cases. It's value is a bitmask, where a set bit results in enabling the corresponding FCLK through the clkc. FPGA clocks are handled following the rules below: If an FCLK is not enabled by bootloaders, that FCLK will be disabled in Linux. Drivers can enable and control it through the CCF as usual. If an FCLK is enabled by bootloaders AND the corresponding bit in the 'fclk-enable' DT property is set, that FCLK will be enabled by the clkc, resulting in an off by one reference count for that clock. Ensuring it will always be running. The default value for 'fclk-enable' is '0xf' (all FCLK's enabled by the bootloader are enabled through the clkc. Signed-off-by: Soren Brinkmann --- .../devicetree/bindings/clock/zynq-7000.txt | 4 ++++ drivers/clk/zynq/clkc.c | 20 +++++++++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt index d99af878f5d7..11fdd146ec83 100644 --- a/Documentation/devicetree/bindings/clock/zynq-7000.txt +++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt @@ -22,6 +22,10 @@ Required properties: Optional properties: - clocks : as described in the clock bindings - clock-names : as described in the clock bindings + - fclk-enable : Bit mask to enable FCLKs in cases no proper CCF compatible + driver is available. Bit [0..3] correspond to FCLK0..FCLK3. The + corresponding FCLK will only be enabled if it is actually + running at boot time. (default = 0xf) Clock inputs: The following strings are optional parameters to the 'clock-names' property in diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 10772aa72e4e..a36fc0f47634 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -102,9 +102,10 @@ static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"}; static void __init zynq_clk_register_fclk(enum zynq_clk fclk, const char *clk_name, void __iomem *fclk_ctrl_reg, - const char **parents) + const char **parents, int enable) { struct clk *clk; + u32 enable_reg; char *mux_name; char *div0_name; char *div1_name; @@ -147,6 +148,12 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, clks[fclk] = clk_register_gate(NULL, clk_name, div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); + enable_reg = readl(fclk_gate_reg) & 1; + if (enable & !enable_reg) { + if (clk_prepare_enable(clks[fclk])) + pr_warn("%s: FCLK%u enable failed\n", __func__, + fclk - fclk0); + } kfree(mux_name); kfree(div0_name); kfree(div1_name); @@ -213,6 +220,7 @@ static void __init zynq_clk_setup(struct device_node *np) int ret; struct clk *clk; char *clk_name; + unsigned int fclk_enable; const char *clk_output_name[clk_max]; const char *cpu_parents[4]; const char *periph_parents[4]; @@ -247,6 +255,10 @@ static void __init zynq_clk_setup(struct device_node *np) ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, tmp); + ret = of_property_read_u32(np, "fclk-enable", &fclk_enable); + if (ret) + fclk_enable = 0xf; + /* PLLs */ clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, SLCR_PLL_STATUS, 0, &armpll_lock); @@ -340,10 +352,12 @@ static void __init zynq_clk_setup(struct device_node *np) clk_prepare_enable(clks[dci]); /* Peripheral clocks */ - for (i = fclk0; i <= fclk3; i++) + for (i = fclk0; i <= fclk3; i++) { + int enable = !!(fclk_enable & BIT(i - fclk0)); zynq_clk_register_fclk(i, clk_output_name[i], SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), - periph_parents); + periph_parents, enable); + } zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, SLCR_LQSPI_CLK_CTRL, periph_parents, 0);