| Message ID | 1381310411-11391-2-git-send-email-josephl@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 2013-10-09 at 17:20 +0800, Joseph Lo wrote: > Adding suspend/resume function for tegra_cpu_car_ops. We only save and > restore the setting of the clock of CoreSight. Other clocks still need > to be taken care by clock driver. > > Cc: Mike Turquette <mturquette@linaro.org> > Signed-off-by: Joseph Lo <josephl@nvidia.com> > --- Sorry. I forgot to mention this series depends on the patch series below. [PATCH 0/5] Tegra124 clock support [PATCH 1/4] clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops > drivers/clk/tegra/clk-tegra124.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c > index c1c9330..66eb1f8a 100644 > --- a/drivers/clk/tegra/clk-tegra124.c > +++ b/drivers/clk/tegra/clk-tegra124.c > @@ -28,6 +28,7 @@ > #include "clk.h" > #include "clk-id.h" > > +#define CLK_SOURCE_CSITE 0x1d4 > #define CLK_SOURCE_EMC 0x19c > #define CLK_SOURCE_XUSB_SS_SRC 0x610 > > @@ -109,6 +110,12 @@ > /* Tegra CPU clock and reset control regs */ > #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 > > +#ifdef CONFIG_PM_SLEEP > +static struct cpu_clk_suspend_context { > + u32 clk_csite_src; > +} tegra124_cpu_clk_sctx; > +#endif > + > static void __iomem *clk_base; > static void __iomem *pmc_base; > > @@ -1139,9 +1146,29 @@ static void tegra124_disable_cpu_clock(u32 cpu) > /* flow controller would take care in the power sequence. */ > } > > +#ifdef CONFIG_PM_SLEEP > +static void tegra124_cpu_clock_suspend(void) > +{ > + /* switch coresite to clk_m, save off original source */ > + tegra124_cpu_clk_sctx.clk_csite_src = > + readl(clk_base + CLK_SOURCE_CSITE); > + writel(3 << 30, clk_base + CLK_SOURCE_CSITE); > +} > + > +static void tegra124_cpu_clock_resume(void) > +{ > + writel(tegra124_cpu_clk_sctx.clk_csite_src, > + clk_base + CLK_SOURCE_CSITE); > +} > +#endif > + > static struct tegra_cpu_car_ops tegra124_cpu_car_ops = { > .wait_for_reset = tegra124_wait_cpu_in_reset, > .disable_clock = tegra124_disable_cpu_clock, > +#ifdef CONFIG_PM_SLEEP > + .suspend = tegra124_cpu_clock_suspend, > + .resume = tegra124_cpu_clock_resume, > +#endif > }; > > static const struct of_device_id pmc_match[] __initconst = {
On 10/09/2013 03:20 AM, Joseph Lo wrote: > Adding suspend/resume function for tegra_cpu_car_ops. We only save and > restore the setting of the clock of CoreSight. Other clocks still need > to be taken care by clock driver. This series also mixes drivers/clk and arch/arm/mach-tegra changes. It looks like there's no build-time dependency though, since this just implements some extra hooks in tegra_cpu_car_ops, so I assume again this clk patch will go through Mike's tree, and the rest of the patches through the Tegra tree. In the future, if there aren't any dependencies, it's best just to send the two sets of changes separately. Acked-by: Stephen Warren <swarren@nvidia.com> (although it'd be nice to have Peter review it too)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index c1c9330..66eb1f8a 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -28,6 +28,7 @@ #include "clk.h" #include "clk-id.h" +#define CLK_SOURCE_CSITE 0x1d4 #define CLK_SOURCE_EMC 0x19c #define CLK_SOURCE_XUSB_SS_SRC 0x610 @@ -109,6 +110,12 @@ /* Tegra CPU clock and reset control regs */ #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 +#ifdef CONFIG_PM_SLEEP +static struct cpu_clk_suspend_context { + u32 clk_csite_src; +} tegra124_cpu_clk_sctx; +#endif + static void __iomem *clk_base; static void __iomem *pmc_base; @@ -1139,9 +1146,29 @@ static void tegra124_disable_cpu_clock(u32 cpu) /* flow controller would take care in the power sequence. */ } +#ifdef CONFIG_PM_SLEEP +static void tegra124_cpu_clock_suspend(void) +{ + /* switch coresite to clk_m, save off original source */ + tegra124_cpu_clk_sctx.clk_csite_src = + readl(clk_base + CLK_SOURCE_CSITE); + writel(3 << 30, clk_base + CLK_SOURCE_CSITE); +} + +static void tegra124_cpu_clock_resume(void) +{ + writel(tegra124_cpu_clk_sctx.clk_csite_src, + clk_base + CLK_SOURCE_CSITE); +} +#endif + static struct tegra_cpu_car_ops tegra124_cpu_car_ops = { .wait_for_reset = tegra124_wait_cpu_in_reset, .disable_clock = tegra124_disable_cpu_clock, +#ifdef CONFIG_PM_SLEEP + .suspend = tegra124_cpu_clock_suspend, + .resume = tegra124_cpu_clock_resume, +#endif }; static const struct of_device_id pmc_match[] __initconst = {
Adding suspend/resume function for tegra_cpu_car_ops. We only save and restore the setting of the clock of CoreSight. Other clocks still need to be taken care by clock driver. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> --- drivers/clk/tegra/clk-tegra124.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)