From patchwork Wed Oct 9 11:20:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 3008391 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2B04DBF924 for ; Wed, 9 Oct 2013 11:38:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 042EA201A4 for ; Wed, 9 Oct 2013 11:38:28 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BD25320173 for ; Wed, 9 Oct 2013 11:38:26 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTs4J-0008Vn-5J; Wed, 09 Oct 2013 11:36:44 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTs3k-0008GK-Sx; Wed, 09 Oct 2013 11:36:09 +0000 Received: from am1ehsobe005.messaging.microsoft.com ([213.199.154.208] helo=am1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTs2z-00088H-24 for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2013 11:35:23 +0000 Received: from mail31-am1-R.bigfish.com (10.3.201.243) by AM1EHSOBE015.bigfish.com (10.3.207.137) with Microsoft SMTP Server id 14.1.225.22; Wed, 9 Oct 2013 11:34:58 +0000 Received: from mail31-am1 (localhost [127.0.0.1]) by mail31-am1-R.bigfish.com (Postfix) with ESMTP id C9FD82A022E; Wed, 9 Oct 2013 11:34:58 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6h1082kzz1de098h1de097h8275bhz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail31-am1 (localhost.localdomain [127.0.0.1]) by mail31-am1 (MessageSwitch) id 1381318497834337_13733; Wed, 9 Oct 2013 11:34:57 +0000 (UTC) Received: from AM1EHSMHS005.bigfish.com (unknown [10.3.201.237]) by mail31-am1.bigfish.com (Postfix) with ESMTP id BE425340053; Wed, 9 Oct 2013 11:34:57 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS005.bigfish.com (10.3.207.105) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 9 Oct 2013 11:34:56 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Wed, 9 Oct 2013 11:34:54 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r99BYWSX015025; Wed, 9 Oct 2013 04:34:51 -0700 From: Dong Aisheng To: Subject: [PATCH 06/10] mmc: sdhci-esdhc-imx: add DDR mode support for mx6 Date: Wed, 9 Oct 2013 19:20:12 +0800 Message-ID: <1381317616-1229-7-git-send-email-b29396@freescale.com> X-Mailer: git-send-email 1.7.2.rc3 In-Reply-To: <1381317616-1229-1-git-send-email-b29396@freescale.com> References: <1381317616-1229-1-git-send-email-b29396@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131009_073521_411416_FC39491B X-CRM114-Status: GOOD ( 12.70 ) X-Spam-Score: -2.6 (--) Cc: shawn.guo@linaro.org, john.tobias.ph@gmail.com, s.hauer@pengutronix.de, anton@enomsg.org, w.sang@pengutronix.de, cjb@laptop.org, b29396@freescale.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When DDR mode is enabled, the initial pre_div should be 2. And the pre_div value should be changed accordingly from ... 02h) Base clock divided by 4 01h) Base clock divided by 2 00h) Base clock divided by 1 to .. 02h) Base clock divided by 8 01h) Base clock divided by 4 00h) Base clock divided by 2 Signed-off-by: Dong Aisheng --- drivers/mmc/host/sdhci-esdhc-imx.c | 17 ++++++++++++++--- 1 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 8721549..b6ae5c1 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -38,6 +38,7 @@ #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) #define ESDHC_WTMK_LVL 0x44 #define ESDHC_MIX_CTRL 0x48 +#define ESDHC_MIX_CTRL_DDREN (1 << 3) #define ESDHC_MIX_CTRL_AC23EN (1 << 7) #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) @@ -117,6 +118,7 @@ struct pltfm_imx_data { WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ } multiblock_status; u32 uhs_mode; + u32 is_ddr; }; static struct platform_device_id imx_esdhc_devtype[] = { @@ -523,8 +525,10 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) * The reset on usdhc fails to clear MIX_CTRL register. * Do it manually here. */ - if (is_imx6_usdhc(imx_data)) + if (is_imx6_usdhc(imx_data)) { writel(0, host->ioaddr + ESDHC_MIX_CTRL); + imx_data->is_ddr = 0; + } } } @@ -568,7 +572,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, goto out; } - if (is_imx6_usdhc(imx_data)) + if (is_imx6_usdhc(imx_data) && !imx_data->is_ddr) pre_div = 1; temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); @@ -586,7 +590,10 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", clock, host->mmc->actual_clock); - pre_div >>= 1; + if (imx_data->is_ddr) + pre_div >>= 2; + else + pre_div >>= 1; div--; temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); @@ -812,6 +819,10 @@ static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) break; case MMC_TIMING_UHS_DDR50: imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; + writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | + ESDHC_MIX_CTRL_DDREN, + host->ioaddr + ESDHC_MIX_CTRL); + imx_data->is_ddr = 1; break; }