From patchwork Fri Oct 11 09:57:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 3021931 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B76649F1E1 for ; Fri, 11 Oct 2013 09:59:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6AE7E2031A for ; Fri, 11 Oct 2013 09:59:33 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6248201ED for ; Fri, 11 Oct 2013 09:59:28 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUZUS-0000Qd-I7; Fri, 11 Oct 2013 09:58:36 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUZUC-0002Tw-O3; Fri, 11 Oct 2013 09:58:20 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUZTu-0002QI-DX for linux-arm-kernel@lists.infradead.org; Fri, 11 Oct 2013 09:58:04 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 11 Oct 2013 02:57:38 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 11 Oct 2013 02:53:26 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 11 Oct 2013 02:53:26 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.327.1; Fri, 11 Oct 2013 02:57:40 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH V2 1/4] clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops Date: Fri, 11 Oct 2013 17:57:29 +0800 Message-ID: <1381485452-3561-2-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1381485452-3561-1-git-send-email-josephl@nvidia.com> References: <1381485452-3561-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131011_055802_636512_8D950671 X-CRM114-Status: GOOD ( 12.78 ) X-Spam-Score: -2.1 (--) Cc: linux-tegra@vger.kernel.org, Peter De Schrijver , Mike Turquette , linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hook the functions for CPU hotplug support. After the CPU is hot unplugged, the flow controller will handle to clock gate the CPU clock. But still need to implement an empty function to avoid warning message. Cc: Mike Turquette Signed-off-by: Joseph Lo --- Cc: Peter De Schrijver This patch depends on the patch series "[PATCH 0/5] Tegra124 clock support" that sent by Peter on 10/4/2013. V2: * no change --- drivers/clk/tegra/clk-tegra124.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 26ba059..c1c9330 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -106,6 +106,9 @@ #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) +/* Tegra CPU clock and reset control regs */ +#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 + static void __iomem *clk_base; static void __iomem *pmc_base; @@ -1120,6 +1123,27 @@ static void __init tegra124_pll_init(void __iomem *clk_base, } +/* Tegra124 CPU clock and reset control functions */ +static void tegra124_wait_cpu_in_reset(u32 cpu) +{ + unsigned int reg; + + do { + reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); + cpu_relax(); + } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ +} + +static void tegra124_disable_cpu_clock(u32 cpu) +{ + /* flow controller would take care in the power sequence. */ +} + +static struct tegra_cpu_car_ops tegra124_cpu_car_ops = { + .wait_for_reset = tegra124_wait_cpu_in_reset, + .disable_clock = tegra124_disable_cpu_clock, +}; + static const struct of_device_id pmc_match[] __initconst = { { .compatible = "nvidia,tegra124-pmc" }, {}, @@ -1202,5 +1226,7 @@ static void __init tegra124_clock_init(struct device_node *np) tegra_add_of_provider(np); tegra_clk_apply_init_table = tegra124_clock_apply_init_table; + + tegra_cpu_car_ops = &tegra124_cpu_car_ops; } CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);