From patchwork Fri Oct 11 11:15:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe PLAGNIOL-VILLARD X-Patchwork-Id: 3023331 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E0EECBF924 for ; Fri, 11 Oct 2013 11:15:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4618B20253 for ; Fri, 11 Oct 2013 11:15:25 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85EEF2024C for ; Fri, 11 Oct 2013 11:15:23 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUagU-0001Yh-LH; Fri, 11 Oct 2013 11:15:06 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUagQ-0005LV-Bv; Fri, 11 Oct 2013 11:15:02 +0000 Received: from 2.mo5.mail-out.ovh.net ([178.33.109.111] helo=mo5.mail-out.ovh.net) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUagA-0005Iw-CO for linux-arm-kernel@lists.infradead.org; Fri, 11 Oct 2013 11:14:48 +0000 Received: from mail94.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo5.mail-out.ovh.net (Postfix) with SMTP id E770EFF8709 for ; Fri, 11 Oct 2013 13:14:24 +0200 (CEST) Received: from b0.ovh.net (HELO queueout) (213.186.33.50) by b0.ovh.net with SMTP; 11 Oct 2013 13:14:23 +0200 Received: from ns203013.ovh.net (HELO localhost) (plagnioj%jcrosoft.com@91.121.171.124) by ns0.ovh.net with SMTP; 11 Oct 2013 13:14:18 +0200 From: Jean-Christophe PLAGNIOL-VILLARD To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] at91: add rtc irq fixup Date: Fri, 11 Oct 2013 13:15:53 +0200 Message-Id: <1381490153-9706-2-git-send-email-plagnioj@jcrosoft.com> X-Mailer: git-send-email 1.8.4.rc3 In-Reply-To: <1381490153-9706-1-git-send-email-plagnioj@jcrosoft.com> References: <1381490153-9706-1-git-send-email-plagnioj@jcrosoft.com> X-Ovh-Tracer-Id: 15963571829908483069 X-Ovh-Remote: 91.121.171.124 (ns203013.ovh.net) X-Ovh-Local: 213.186.33.20 (ns0.ovh.net) X-OVH-SPAMSTATE: OK X-OVH-SPAMSCORE: -100 X-OVH-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeiledrvdefucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-Spam-Check: DONE|U 0.5/N X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeiledrvdefucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131011_071447_025032_8FB3F9E2 X-CRM114-Status: GOOD ( 19.14 ) X-Spam-Score: -1.9 (-) Cc: Nicolas Ferre , Johan Hovold , Jean-Christophe PLAGNIOL-VILLARD X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the irq can still be on after a reset or power on as the IP are powered by the backup power. This could lead to an interrupt dead lock when the kernel boot. So disable them before booting. Handle it in C as the DT may not provide or enable the RTC node but we still need the fixup. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Cc: Nicolas Ferre Cc: Johan Hovold --- arch/arm/mach-at91/at91sam9g45.c | 1 + arch/arm/mach-at91/at91sam9n12.c | 6 ++++++ arch/arm/mach-at91/at91sam9rl.c | 1 + arch/arm/mach-at91/at91sam9x5.c | 6 ++++++ arch/arm/mach-at91/generic.h | 1 + arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 ++ arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 ++ arch/arm/mach-at91/include/mach/sama5d3.h | 2 ++ arch/arm/mach-at91/irq_fixup.c | 25 +++++++++++++++++++++++++ arch/arm/mach-at91/sama5d3.c | 6 ++++++ 10 files changed, 52 insertions(+) diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index b3e2693..654f9ab 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -375,6 +375,7 @@ static void __init at91sam9g45_ioremap_registers(void) static void __init at91sam9g45_initialize(void) { at91_rtt_irq_fixup(AT91SAM9G45_BASE_RTT); + at91_rtc_irq_fixup(AT91SAM9G45_BASE_RTC); arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9g45_restart; diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index c7d670d1..98a1739 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -223,7 +223,13 @@ static void __init at91sam9n12_map_io(void) at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); } +static void __init at91sam9n12_initialize(void) +{ + at91_rtc_irq_fixup(AT91SAM9N12_BASE_RTC); +} + AT91_SOC_START(at91sam9n12) .map_io = at91sam9n12_map_io, .register_clocks = at91sam9n12_register_clocks, + .init = at91sam9n12_initialize, AT91_SOC_END diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 01feae9..6acd6a4 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -292,6 +292,7 @@ static void __init at91sam9rl_ioremap_registers(void) static void __init at91sam9rl_initialize(void) { at91_rtt_irq_fixup(AT91SAM9RL_BASE_RTT); + at91_rtc_irq_fixup(AT91SAM9RL_BASE_RTC); arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9_alt_restart; diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 916e5a1..26ef20a 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -322,6 +322,11 @@ static void __init at91sam9x5_map_io(void) at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE); } +static void __init at91sam9x5_initialize(void) +{ + at91_rtc_irq_fixup(AT91SAM9X5_BASE_RTC); +} + /* -------------------------------------------------------------------- * Interrupt initialization * -------------------------------------------------------------------- */ @@ -329,4 +334,5 @@ static void __init at91sam9x5_map_io(void) AT91_SOC_START(at91sam9x5) .map_io = at91sam9x5_map_io, .register_clocks = at91sam9x5_register_clocks, + .init = at91sam9x5_initialize, AT91_SOC_END diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index c7ad514..7d377f3 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -36,6 +36,7 @@ extern int __init at91_aic5_of_init(struct device_node *node, struct device_node *parent); void at91_rtt_irq_fixup(uint32_t addr); +void at91_rtc_irq_fixup(uint32_t addr); /* Timer */ extern void at91rm9200_ioremap_st(u32 addr); diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h index d374b87..6a1d457 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h +++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h @@ -48,6 +48,8 @@ #define AT91SAM9N12_BASE_USART2 0xf8024000 #define AT91SAM9N12_BASE_USART3 0xf8028000 +#define AT91SAM9N12_BASE_RTC 0xfffffeb0 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index c75ee19..24e281c 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -54,6 +54,8 @@ #define AT91SAM9X5_BASE_USART1 0xf8020000 #define AT91SAM9X5_BASE_USART2 0xf8024000 +#define AT91SAM9X5_BASE_RTC 0xfffffeb0 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 31096a8..b5d045e 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -72,6 +72,8 @@ #define SAMA5D3_BASE_USART2 0xf8020000 #define SAMA5D3_BASE_USART3 0xf8024000 +#define SAMA5D3_BASE_RTC 0xfffffeb0 + /* * Internal Memory */ diff --git a/arch/arm/mach-at91/irq_fixup.c b/arch/arm/mach-at91/irq_fixup.c index a93588f..38bdfec 100644 --- a/arch/arm/mach-at91/irq_fixup.c +++ b/arch/arm/mach-at91/irq_fixup.c @@ -31,3 +31,28 @@ void at91_rtt_irq_fixup(uint32_t addr) writel(mr &~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN), reg); iounmap(base); } + + +#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */ + +/* + * As the RTC is powered by the backup power so if the interrupt + * is still on when the kernel start, the kernel will end up with + * dead lock interrupt that it can not clear. Because the interrupt line is + * shared with the basic timer (PIT) on AT91_ID_SYS. + */ +void at91_rtc_irq_fixup(uint32_t addr) +{ + void __iomem *reg; + void __iomem *base; + + base = ioremap(addr, 256); + if (!base) + return; + + reg = base + AT91_RTC_IDR; + + writel(0x5, reg); + + iounmap(base); +} diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c index 4012797..548b37d 100644 --- a/arch/arm/mach-at91/sama5d3.c +++ b/arch/arm/mach-at91/sama5d3.c @@ -371,7 +371,13 @@ static void __init sama5d3_map_io(void) at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); } +static void __init sama5d3_initialize(void) +{ + at91_rtc_irq_fixup(SAMA5D3_BASE_RTC); +} + AT91_SOC_START(sama5d3) .map_io = sama5d3_map_io, .register_clocks = sama5d3_register_clocks, + .init = sama5d3_initialize, AT91_SOC_END