From patchwork Fri Oct 11 21:45:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 3029561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CBF889F1E1 for ; Fri, 11 Oct 2013 21:52:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0D20E20379 for ; Fri, 11 Oct 2013 21:52:44 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB19B20373 for ; Fri, 11 Oct 2013 21:52:42 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUkcT-0003eT-85; Fri, 11 Oct 2013 21:51:37 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUkXY-0000K2-OJ; Fri, 11 Oct 2013 21:46:32 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUkXC-0000G7-Kd for linux-arm-kernel@lists.infradead.org; Fri, 11 Oct 2013 21:46:12 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 11 Oct 2013 14:45:45 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 11 Oct 2013 14:45:49 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 11 Oct 2013 14:45:49 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.327.1; Fri, 11 Oct 2013 14:45:49 -0700 From: Alexandre Courbot To: Stephen Warren Subject: [PATCH v8 4/5] ARM: tegra: set CPU reset handler with firmware op Date: Fri, 11 Oct 2013 14:45:37 -0700 Message-ID: <1381527938-22840-5-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1381527938-22840-1-git-send-email-acourbot@nvidia.com> References: <1381527938-22840-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131011_174610_885342_944882C9 X-CRM114-Status: GOOD ( 12.91 ) X-Spam-Score: -2.1 (--) Cc: Mark Rutland , devicetree@vger.kernel.org, Kevin Hilman , Russell King , Pawel Moll , Arnd Bergmann , Ian Campbell , Tomasz Figa , linux-kernel@vger.kernel.org, Rob Herring , linux-tegra@vger.kernel.org, Alexandre Courbot , Olof Johansson , Dave Martin , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use a firmware operation to set the CPU reset handler and only resort to doing it ourselves if there is none defined. This supports the booting of secondary CPUs on devices using a TrustZone secure monitor. Signed-off-by: Alexandre Courbot Reviewed-by: Tomasz Figa Reviewed-by: Stephen Warren --- arch/arm/mach-tegra/reset.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index e282395..368af0a 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -21,6 +21,7 @@ #include #include +#include #include "iomap.h" #include "irammap.h" @@ -65,6 +66,7 @@ static void __init tegra_cpu_reset_handler_enable(void) void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); const u32 reset_address = TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset; + int err; BUG_ON(is_enabled); BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); @@ -72,9 +74,18 @@ static void __init tegra_cpu_reset_handler_enable(void) memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, tegra_cpu_reset_handler_size); - tegra_cpu_reset_handler_set(reset_address); - - is_enabled = true; + err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); + switch (err) { + case -ENOSYS: + tegra_cpu_reset_handler_set(reset_address); + /* pass-through */ + case 0: + is_enabled = true; + break; + default: + pr_crit("Cannot set CPU reset handler: %d\n", err); + BUG(); + } } void __init tegra_cpu_reset_handler_init(void)