From patchwork Mon Oct 14 19:47:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3038531 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 389069F243 for ; Mon, 14 Oct 2013 19:49:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2415820213 for ; Mon, 14 Oct 2013 19:49:17 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 04D41201D3 for ; Mon, 14 Oct 2013 19:49:16 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VVo8A-0005Yk-SI; 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envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail34-db9 (localhost.localdomain [127.0.0.1]) by mail34-db9 (MessageSwitch) id 1381780076988391_1924; Mon, 14 Oct 2013 19:47:56 +0000 (UTC) Received: from DB9EHSMHS017.bigfish.com (unknown [10.174.16.250]) by mail34-db9.bigfish.com (Postfix) with ESMTP id EA4FEDC0041; Mon, 14 Oct 2013 19:47:56 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by DB9EHSMHS017.bigfish.com (10.174.14.27) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 14 Oct 2013 19:47:51 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Mon, 14 Oct 2013 12:36:28 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.65]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r9EJlj86007913; Mon, 14 Oct 2013 12:47:48 -0700 (PDT) From: To: Subject: [RESEND PATCHv2 2/3] mmc: dw_mmc-socfpga: Clean up SOCFPGA platform specific functionality Date: Mon, 14 Oct 2013 14:47:30 -0500 Message-ID: <1381780051-1826-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381780051-1826-1-git-send-email-dinguyen@altera.com> References: <1381780051-1826-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131014_154822_486481_2A685140 X-CRM114-Status: GOOD ( 16.53 ) X-Spam-Score: 1.1 (+) Cc: Mark Rutland , devicetree@vger.kernel.org, Arnd Bergmann , Pawel Moll , Stephen Warren , Seungwon Jeon , Pavel Machek , linux-mmc@vger.kernel.org, Rob Herring , Jaehoon Chung , linux-arm-kernel@lists.infradead.org, Olof Johansson , Chris Ball , Dinh Nguyen , Ian Campbell X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The SDR timing registers for the SD/MMC IP block for SOCFPGA is located in the system manager. This system manager IP block is located outside of the SD IP block itself. Therefore, the function to set the SDR timing register should be in the platform specific code so that the SD driver can be autonomous of any future System Manager changes. Also, there is no need for "altr,dw-mshc-ciu-div" as the driver can get the value of the CIU clock from the common clock API. Signed-off-by: Dinh Nguyen Cc: Pavel Machek CC: Arnd Bergmann CC: Olof Johansson Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell Cc: Chris Ball Cc: Jaehoon Chung Cc: Seungwon Jeon Cc: devicetree@vger.kernel.org Cc: linux-mmc@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- v2: - Let the mmc driver walk the DTB to get the SDR values --- drivers/mmc/host/dw_mmc-socfpga.c | 38 +++++++++---------------------------- 1 file changed, 9 insertions(+), 29 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c index 14b5961..3be2e2a 100644 --- a/drivers/mmc/host/dw_mmc-socfpga.c +++ b/drivers/mmc/host/dw_mmc-socfpga.c @@ -24,16 +24,12 @@ #include "dw_mmc.h" #include "dw_mmc-pltfm.h" -#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 -#define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7 -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) +extern void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel); /* SOCFPGA implementation specific driver private data */ struct dw_mci_socfpga_priv_data { - u8 ciu_div; /* card interface unit divisor */ - u32 hs_timing; /* bitmask for CIU clock phase shift */ - struct regmap *sysreg; /* regmap for system manager register */ + u32 drvsel; /*Phase shift for the Drive clock, or tx mode.*/ + u32 smplsel; /*Phase shift for the Sample clock, or rx mode.*/ }; static int dw_mci_socfpga_priv_init(struct dw_mci *host) @@ -45,14 +41,7 @@ static int dw_mci_socfpga_priv_init(struct dw_mci *host) dev_err(host->dev, "mem alloc failed for private data\n"); return -ENOMEM; } - - priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(priv->sysreg)) { - dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n"); - return PTR_ERR(priv->sysreg); - } host->priv = priv; - return 0; } @@ -61,20 +50,15 @@ static int dw_mci_socfpga_setup_clock(struct dw_mci *host) struct dw_mci_socfpga_priv_data *priv = host->priv; clk_disable_unprepare(host->ciu_clk); - regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, - priv->hs_timing); + socfpga_sysmgr_set_dwmmc_drvsel_smpsel(priv->drvsel, priv->smplsel); clk_prepare_enable(host->ciu_clk); - host->bus_hz /= (priv->ciu_div + 1); return 0; } static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr) { - struct dw_mci_socfpga_priv_data *priv = host->priv; - - if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK) - *cmdr |= SDMMC_CMD_USE_HOLD_REG; + *cmdr |= SDMMC_CMD_USE_HOLD_REG; } static int dw_mci_socfpga_parse_dt(struct dw_mci *host) @@ -82,20 +66,16 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host) struct dw_mci_socfpga_priv_data *priv = host->priv; struct device_node *np = host->dev->of_node; u32 timing[2]; - u32 div = 0; int ret; - ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div); - if (ret) - dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1"); - priv->ciu_div = div; - ret = of_property_read_u32_array(np, - "altr,dw-mshc-sdr-timing", timing, 2); + "samsung,dw-mshc-sdr-timing", timing, 2); if (ret) return ret; - priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); + priv->drvsel = timing[0]; + priv->smplsel = timing[1]; + return 0; }