From patchwork Tue Oct 15 17:41:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 3046911 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 47C1A9F2B6 for ; Tue, 15 Oct 2013 17:44:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E2D120439 for ; Tue, 15 Oct 2013 17:44:49 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BAC2B20114 for ; Tue, 15 Oct 2013 17:44:47 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VW8eH-0000m2-5k; Tue, 15 Oct 2013 17:43:14 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VW8dq-0007pz-Uf; Tue, 15 Oct 2013 17:42:46 +0000 Received: from mailout3.w1.samsung.com ([210.118.77.13]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VW8dG-0007jG-23 for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2013 17:42:11 +0000 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MUQ00HAT159VQC0@mailout3.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2013 18:41:33 +0100 (BST) X-AuditID: cbfec7f4-b7f0a6d000007b1b-16-525d7e4df727 Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id B9.07.31515.D4E7D525; Tue, 15 Oct 2013 18:41:33 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MUQ0039B155K720@eusync1.samsung.com>; Tue, 15 Oct 2013 18:41:33 +0100 (BST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 3/7] clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domain Date: Tue, 15 Oct 2013 19:41:17 +0200 Message-id: <1381858881-25611-4-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.3.2 In-reply-to: <1381858881-25611-1-git-send-email-t.figa@samsung.com> References: <1381858881-25611-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrAJMWRmVeSWpSXmKPExsVy+t/xy7q+dbFBBhs/mFn0LrjKZnG26Q27 xabH11gtZpzfx2TxdMJFNovDb9pZLdbPeM3iwO5x59oeNo/NS+o9+rasYvT4vEkugCWKyyYl NSezLLVI3y6BK2PWlt9MBbtkKlov8TcwLpLoYuTkkBAwkfj3/BUzhC0mceHeerYuRi4OIYGl jBKXbixlhHD6mCSWLfjMClLFJqAm8bnhERuILSKgKvG5bQE7SBGzwBdGiacHtrGDJIQFYiRW X/8INpYFqOjI3eNgcV4BJ4nLnZ+YINYpSCz7shashlPAWeL6w0lgNUJANRcPPWSdwMi7gJFh FaNoamlyQXFSeq6hXnFibnFpXrpecn7uJkZIKH3Zwbj4mNUhRgEORiUe3hNRsUFCrIllxZW5 hxglOJiVRHg1q4FCvCmJlVWpRfnxRaU5qcWHGJk4OKUaGNsWVy4Qklsf0LVu09yuCxt5Ds49 deTWNIYL07IN/smFPFpft3nRtUMytze+ilpjfSOo/daWYx5B2p/iL1Q86rnwKLogfenvX0qR B9gWfbyiUqWpdmDFvLeChhPEmAzDNk/qNFjLu2ae4tYXmUodFWU8s8I15/VXLdS8M93xycR2 E9YUJeazzNxKLMUZiYZazEXFiQCrDdDFAwIAAA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131015_134210_229630_AE1726AA X-CRM114-Status: UNSURE ( 7.50 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -7.4 (-------) Cc: Kukjin Kim , Mike Turquette , Tomasz Figa , Kyungmin Park , Sylwester Nawrocki , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions of GSCL domain gate clocks to use it as their parent, as specified in SoC documentation. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos5250.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index ce33a3f..f91e77d 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -36,6 +36,7 @@ #define GPLL_CON0 0x10150 #define SRC_TOP0 0x10210 #define SRC_TOP2 0x10218 +#define SRC_TOP3 0x1021c #define SRC_GSCL 0x10220 #define SRC_DISP1_0 0x1022c #define SRC_MAU 0x10240 @@ -138,6 +139,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = { SRC_CORE1, SRC_TOP0, SRC_TOP2, + SRC_TOP3, SRC_GSCL, SRC_DISP1_0, SRC_MAU, @@ -194,6 +196,7 @@ PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; +PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", @@ -269,6 +272,8 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(none, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), MUX(none, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), + MUX(none, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), + MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), @@ -480,16 +485,20 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), - GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0), - GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0), - GATE(gscl2, "gscl2", "div_aclk266", GATE_IP_GSCL, 2, 0, 0), - GATE(gscl3, "gscl3", "div_aclk266", GATE_IP_GSCL, 3, 0, 0), + GATE(gscl0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0, 0), + GATE(gscl1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0, 0), + GATE(gscl2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0, 0), + GATE(gscl3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, 0), GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), - GATE(smmu_gscl0, "smmu_gscl0", "div_aclk266", GATE_IP_GSCL, 7, 0, 0), - GATE(smmu_gscl1, "smmu_gscl1", "div_aclk266", GATE_IP_GSCL, 8, 0, 0), - GATE(smmu_gscl2, "smmu_gscl2", "div_aclk266", GATE_IP_GSCL, 9, 0, 0), - GATE(smmu_gscl3, "smmu_gscl3", "div_aclk266", GATE_IP_GSCL, 10, 0, 0), + GATE(smmu_gscl0, "smmu_gscl0", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 7, 0, 0), + GATE(smmu_gscl1, "smmu_gscl1", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 8, 0, 0), + GATE(smmu_gscl2, "smmu_gscl2", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 9, 0, 0), + GATE(smmu_gscl3, "smmu_gscl3", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 10, 0, 0), GATE(fimd1, "fimd1", "div_aclk200", GATE_IP_DISP1, 0, 0, 0), GATE(mie1, "mie1", "div_aclk200", GATE_IP_DISP1, 1, 0, 0),