From patchwork Thu Oct 17 00:32:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3058301 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 50DCF9F3E3 for ; Thu, 17 Oct 2013 00:33:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3ADBC20425 for ; Thu, 17 Oct 2013 00:33:22 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 34B7820343 for ; Thu, 17 Oct 2013 00:33:20 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VWbWf-0008NM-9f; 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envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail1-db9 (localhost.localdomain [127.0.0.1]) by mail1-db9 (MessageSwitch) id 1381969966335007_27464; Thu, 17 Oct 2013 00:32:46 +0000 (UTC) Received: from DB9EHSMHS027.bigfish.com (unknown [10.174.16.240]) by mail1-db9.bigfish.com (Postfix) with ESMTP id 4B31FD00049; Thu, 17 Oct 2013 00:32:46 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by DB9EHSMHS027.bigfish.com (10.174.14.37) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 17 Oct 2013 00:32:45 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Wed, 16 Oct 2013 17:21:21 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.65]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r9H0Wd7r023927; Wed, 16 Oct 2013 17:32:42 -0700 (PDT) From: To: Subject: [PATCH 1/4] clk: socfpga: Add a clock driver for SOCFPGA's system manager Date: Wed, 16 Oct 2013 19:32:38 -0500 Message-ID: <1381969961-12679-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381969961-12679-1-git-send-email-dinguyen@altera.com> References: <1381969961-12679-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131016_203310_642335_F3BBC3B4 X-CRM114-Status: GOOD ( 22.06 ) X-Spam-Score: 1.1 (+) Cc: Mark Rutland , devicetree@vger.kernel.org, Mike Turquette , Pawel Moll , Arnd Bergmann , Stephen Warren , Seungwon Jeon , Pavel Machek , linux-mmc@vger.kernel.org, Rob Herring , Jaehoon Chung , linux-arm-kernel@lists.infradead.org, Olof Johansson , Chris Ball , Dinh Nguyen , Ian Campbell X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The system manager is an IP block on the SOCFPGA platform. The system manager contains registers that control other IPs on the platform. One of them is the SD/MMC IP. The system manager contains a register that controls the clock phase of the SD/MMC CIU. This patch adds a clock driver that the SD/MMC driver can use by calling the common clock API in order to set the appropriate register in the system manager. Signed-off-by: Dinh Nguyen Cc: Pavel Machek CC: Arnd Bergmann Cc: Mike Turquette CC: Olof Johansson Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell Cc: Chris Ball Cc: Jaehoon Chung Cc: Seungwon Jeon Cc: devicetree@vger.kernel.org Cc: linux-mmc@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- drivers/clk/socfpga/Makefile | 2 +- drivers/clk/socfpga/clk-sysmgr.c | 91 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/socfpga/clk-sysmgr.c diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index 0303c0b..cfceabc 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -1 +1 @@ -obj-y += clk.o +obj-y += clk.o clk-sysmgr.o diff --git a/drivers/clk/socfpga/clk-sysmgr.c b/drivers/clk/socfpga/clk-sysmgr.c new file mode 100644 index 0000000..0e13290 --- /dev/null +++ b/drivers/clk/socfpga/clk-sysmgr.c @@ -0,0 +1,91 @@ +/* + * Copyright 2013 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include + +extern void __iomem *sys_manager_base_addr; + +/* SDMMC Group for System Manager defines */ +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) + +struct socfpga_sysmgr { + struct clk_hw hw; + void __iomem *reg; +}; +#define to_sysmgr_clk(p) container_of(p, struct socfpga_sysmgr, hw) + +static int sysmgr_set_dwmmc_drvsel_smpsel(struct clk_hw *hwclk) +{ + struct device_node *np; + struct socfpga_sysmgr *socfpga_sysmgr = to_sysmgr_clk(hwclk); + u32 timing[2]; + u32 hs_timing; + + np = of_find_compatible_node(NULL, NULL, "altr,socfpga-dw-mshc"); + of_property_read_u32_array(np, "samsung,dw-mshc-sdr-timing", timing, 2); + hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[1], timing[0]); + writel(hs_timing, socfpga_sysmgr->reg); + return 0; +} + +static const struct clk_ops clk_sysmgr_sdmmc_ops = { + .enable = sysmgr_set_dwmmc_drvsel_smpsel, +}; + +static void __init socfpga_sysmgr_init(struct device_node *node, const struct clk_ops *ops) +{ + u32 reg; + struct clk *clk; + struct socfpga_sysmgr *socfpga_sysmgr; + const char *clk_name = node->name; + struct clk_init_data init; + int rc; + + rc = of_property_read_u32(node, "reg", ®); + if (WARN_ON(rc)) + return; + + socfpga_sysmgr = kzalloc(sizeof(*socfpga_sysmgr), GFP_KERNEL); + if (WARN_ON(!socfpga_sysmgr)) + return; + + socfpga_sysmgr->reg = sys_manager_base_addr + reg; + + init.name = clk_name; + init.ops = ops; + init.flags = 0; + init.num_parents = 0; + + socfpga_sysmgr->hw.init = &init; + clk = clk_register(NULL, &socfpga_sysmgr->hw); + if (WARN_ON(IS_ERR(clk))) { + kfree(socfpga_sysmgr); + return; + } + rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (WARN_ON(rc)) + return; +} + +static void __init sysmgr_init(struct device_node *node) +{ + socfpga_sysmgr_init(node, &clk_sysmgr_sdmmc_ops); +} +CLK_OF_DECLARE(sysmgr, "altr,sysmgr-sdmmc-sdr", sysmgr_init);