From patchwork Thu Oct 17 00:32:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3058351 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DBDBCBF924 for ; Thu, 17 Oct 2013 00:35:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 02B3320394 for ; Thu, 17 Oct 2013 00:35:27 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2A6420343 for ; Thu, 17 Oct 2013 00:35:25 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VWbXd-0000ZW-T7; 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envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail101-db9 (localhost.localdomain [127.0.0.1]) by mail101-db9 (MessageSwitch) id 1381969970366160_25915; Thu, 17 Oct 2013 00:32:50 +0000 (UTC) Received: from DB9EHSMHS019.bigfish.com (unknown [10.174.16.240]) by mail101-db9.bigfish.com (Postfix) with ESMTP id 4DF1E340066; Thu, 17 Oct 2013 00:32:50 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by DB9EHSMHS019.bigfish.com (10.174.14.29) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 17 Oct 2013 00:32:48 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Wed, 16 Oct 2013 17:21:23 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.65]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r9H0Wd7s023927; Wed, 16 Oct 2013 17:32:44 -0700 (PDT) From: To: Subject: [PATCH 2/4] arm: dts: Add a system manager compatible property Date: Wed, 16 Oct 2013 19:32:39 -0500 Message-ID: <1381969961-12679-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381969961-12679-1-git-send-email-dinguyen@altera.com> References: <1381969961-12679-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131016_203339_983931_6A47891D X-CRM114-Status: GOOD ( 12.41 ) X-Spam-Score: 1.1 (+) Cc: Mark Rutland , devicetree@vger.kernel.org, Mike Turquette , Pawel Moll , Arnd Bergmann , Stephen Warren , Seungwon Jeon , Pavel Machek , linux-mmc@vger.kernel.org, Rob Herring , Jaehoon Chung , linux-arm-kernel@lists.infradead.org, Olof Johansson , Chris Ball , Dinh Nguyen , Ian Campbell X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The "altr,sysmgr-sdmmc-sdr" compatible property is used for the SOCFPGA clk-sysmgr driver. This property represents the register inside the system manager that controls the clock phase of the SD/MMC driver. Signed-off-by: Dinh Nguyen Cc: Pavel Machek CC: Arnd Bergmann Cc: Mike Turquette CC: Olof Johansson Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell Cc: Chris Ball Cc: Jaehoon Chung Cc: Seungwon Jeon Cc: devicetree@vger.kernel.org Cc: linux-mmc@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- .../bindings/arm/altera/socfpga-system.txt | 10 ++++++++++ arch/arm/boot/dts/socfpga.dtsi | 12 ++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt index f4d04a0..7a6c7ed 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt @@ -5,9 +5,19 @@ Required properties: - reg : Should contain 1 register ranges(address and length) - cpu1-start-addr : CPU1 start address in hex. +Optional properties: +- compatible = "altr,sysmgr-sdmmc-sdr". This compatible property is used +to represent the clock phase settings for the SD/MMC IP. + Example: sysmgr@ffd08000 { compatible = "altr,sys-mgr"; reg = <0xffd08000 0x1000>; cpu1-start-addr = <0xffd080c4>; + + sysmgr_sdr_mmc: sysmgr_sdr_mmc { + #clock-cells = <0>; + compatible = "altr,sysmgr-sdmmc-sdr"; + reg = <0x108 1>; + }; }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index e273fa9..0662d04 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -521,8 +521,16 @@ }; sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; - reg = <0xffd08000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "altr,sys-mgr"; + reg = <0xffd08000 0x4000>; + + sysmgr_sdr_mmc: sysmgr_sdr_mmc { + #clock-cells = <0>; + compatible = "altr,sysmgr-sdmmc-sdr"; + reg = <0x108 1>; }; + }; }; };