| Message ID | 1382137374-21251-10-git-send-email-ezequiel.garcia@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Oct 18, 2013 at 08:02:36PM -0300, Ezequiel Garcia wrote: > > - switch (host->page_size) { > + switch (info->fifo_size) { > case 2048: there is a item in the builtin_flash_types: { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, The original host->page_size could be 4096, how can the old code support this nand with page-size is 4096? thanks Huang Shijie
On Sun, Nov 03, 2013 at 05:36:50PM -0500, Huang Shijie wrote: > On Fri, Oct 18, 2013 at 08:02:36PM -0300, Ezequiel Garcia wrote: > > > > - switch (host->page_size) { > > + switch (info->fifo_size) { > > case 2048: > > there is a item in the builtin_flash_types: > { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, > > The original host->page_size could be 4096, how can the old code support > this nand with page-size is 4096? > Ah, nice catch. I completely missed that line! I've rechecked the PXA3xx spec. but it makes no mention to supporting 4096 (and it doesn't mention the FIFO buffer's size). On the other side, and AFAIK, the 'splitted' command semantics in the NFCv2 (the one I'm working on) was added specifically to support page-size of 4096 and 8192. In other words, I'm not sure how could the old code support 4096! The support was adding long ago, in this commit: commit d3490dfdbc453a16bc7f3cff731c9f7851735ab3 Author: Haojian Zhuang <haojian.zhuang@marvell.com> Date: Thu Sep 10 14:33:30 2009 +0800 pxa3xx_nand: add new nand chip support Support samsung 2GbX8 and 32GbX8 nand flash. Support micron 4GbX8 and 4GbX16 nand flash. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com> So, maybe they can provide some answers. Haojian? Eric?
On 11/04/2013 08:13 PM, Ezequiel Garcia wrote: > On Sun, Nov 03, 2013 at 05:36:50PM -0500, Huang Shijie wrote: >> On Fri, Oct 18, 2013 at 08:02:36PM -0300, Ezequiel Garcia wrote: >>> >>> - switch (host->page_size) { >>> + switch (info->fifo_size) { >>> case 2048: >> >> there is a item in the builtin_flash_types: >> { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, >> >> The original host->page_size could be 4096, how can the old code support >> this nand with page-size is 4096? >> > > Ah, nice catch. I completely missed that line! > > I've rechecked the PXA3xx spec. but it makes no mention to supporting > 4096 (and it doesn't mention the FIFO buffer's size). > > On the other side, and AFAIK, the 'splitted' command semantics in the > NFCv2 (the one I'm working on) was added specifically to support > page-size of 4096 and 8192. > > In other words, I'm not sure how could the old code support 4096! > The support was adding long ago, in this commit: > > commit d3490dfdbc453a16bc7f3cff731c9f7851735ab3 > Author: Haojian Zhuang <haojian.zhuang@marvell.com> > Date: Thu Sep 10 14:33:30 2009 +0800 > > pxa3xx_nand: add new nand chip support > > Support samsung 2GbX8 and 32GbX8 nand flash. > Support micron 4GbX8 and 4GbX16 nand flash. > > Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> > Signed-off-by: Eric Miao <eric.y.miao@gmail.com> > > So, maybe they can provide some answers. Haojian? Eric? > Hi Ezequiel, I can't remember all details. The main problem is that I failed to find the flash datasheet. Regards Haojian
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 1e2f4ae..fe2e27c 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -199,8 +199,8 @@ struct pxa3xx_nand_info { int use_spare; /* use spare ? */ int is_ready; - unsigned int page_size; /* page size of attached chip */ - unsigned int data_size; /* data size in FIFO */ + unsigned int fifo_size; /* max. data size in the FIFO */ + unsigned int data_size; /* data to be read from FIFO */ unsigned int oob_size; int retcode; @@ -305,16 +305,15 @@ static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) { - struct pxa3xx_nand_host *host = info->host[info->cs]; int oob_enable = info->reg_ndcr & NDCR_SPARE_EN; - info->data_size = host->page_size; + info->data_size = info->fifo_size; if (!oob_enable) { info->oob_size = 0; return; } - switch (host->page_size) { + switch (info->fifo_size) { case 2048: info->oob_size = (info->use_ecc) ? 40 : 64; break; @@ -929,9 +928,12 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) uint32_t ndcr = nand_readl(info, NDCR); if (ndcr & NDCR_PAGE_SZ) { + /* Controller's FIFO size */ + info->fifo_size = 2048; host->page_size = 2048; host->read_id_bytes = 4; } else { + info->fifo_size = 512; host->page_size = 512; host->read_id_bytes = 2; }
Introduce a fifo_size field to represent the size of the controller's FIFO buffer, and use it to distinguish that size from the amount of data bytes to be read from the FIFO. This is important to support devices with pages larger than the controller's internal FIFO, that need to read the pages in FIFO-sized chunks. In particular, the current code is at least confusing, for it mixes all the different sizes involved: FIFO size, page size and data size. This commit starts the cleaning by removing the info->page_size field that is not currently used. The host->page_size field should also be removed and use always mtd->writesize instead. Follow up commits will clean this up. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> --- drivers/mtd/nand/pxa3xx_nand.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)