From patchwork Tue Oct 22 09:08:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 3081541 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6C91ABF924 for ; Tue, 22 Oct 2013 09:11:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4CCAE2048E for ; Tue, 22 Oct 2013 09:11:05 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0075C2046F for ; Tue, 22 Oct 2013 09:11:04 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VYXyW-0000vL-9e; Tue, 22 Oct 2013 09:10:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VYXyI-0006B7-9S; Tue, 22 Oct 2013 09:09:50 +0000 Received: from mail-wg0-f42.google.com ([74.125.82.42]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VYXxs-00065z-1Z for linux-arm-kernel@lists.infradead.org; Tue, 22 Oct 2013 09:09:29 +0000 Received: by mail-wg0-f42.google.com with SMTP id n12so5663572wgh.3 for ; Tue, 22 Oct 2013 02:09:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Rf3L8zQPDSnWDjuGqaUZoYEPyWfQ7PGHjTWIQzBRsxA=; b=DkBR9XZ3twrDWqd8EVBTOHCk+VAiTSxSKsjTZQYmCAfK1WE6fl1phlJsOVKSdc5X9y rZOAsA6it1WGAsA5b87bNpTF+YwUJ/LvASzY/OD3LCiIO3EoLC2Tb1d1Vbrq/vaEk8GS i4bKIShCBefWVy4vo3XlviDPG6FMyEbsKFO4OZ9+w9cixXW6ioFasfdcmdfSrHmr0GfE Xpi0qN0vC25mpK8EPbP+TDqyVO8U644haZW8ovTtE5f2036Y8ID5Gk88Uue8ng/3ksGH 28alzmL1c5wGbtF2vObTQwvcQNrU1X8bM9RlQsHDoHHCoCDIi9XPelzMO0yp9Iou/T6c ws9Q== X-Gm-Message-State: ALoCoQmE2ySOynV7eQeD0FZ4MsVxQjJEuqznOpYVsTNVY2IXKSG9HhyzOL51Xg6WBBprr6r4KeNt X-Received: by 10.194.2.108 with SMTP id 12mr683228wjt.64.1382432942385; Tue, 22 Oct 2013 02:09:02 -0700 (PDT) Received: from hsia.quadriga.com (ip-77-221-165-98.dsl.twang.net. [77.221.165.98]) by mx.google.com with ESMTPSA id ma3sm4302512wic.1.2013.10.22.02.09.01 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 22 Oct 2013 02:09:02 -0700 (PDT) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu Subject: [PATCH RESEND v2 4/8] irqchip: arm-gic: Define additional MMIO offsets and masks Date: Tue, 22 Oct 2013 10:08:39 +0100 Message-Id: <1382432923-61267-5-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1382432923-61267-1-git-send-email-christoffer.dall@linaro.org> References: <1382432923-61267-1-git-send-email-christoffer.dall@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131022_050924_244646_8A566E65 X-CRM114-Status: UNSURE ( 9.24 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.1 (/) Cc: Christoffer Dall , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, SUSPICIOUS_RECIPS, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define CPU interface offsets for the GICC_ABPR, GICC_APR, and GICC_IIDR registers. Define distributor registers for the GICD_SPENDSGIR and the GICD_CPENDSGIR. KVM/ARM needs to know about these definitions to fully support save/restore of the VGIC. Also define some masks and shifts for the various GICH_VMCR fields. Cc: Thomas Gleixner Signed-off-by: Christoffer Dall Reviewed-by: Alexander Graf --- include/linux/irqchip/arm-gic.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 0e5d9ec..28b28fc 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -17,6 +17,9 @@ #define GIC_CPU_EOI 0x10 #define GIC_CPU_RUNNINGPRI 0x14 #define GIC_CPU_HIGHPRI 0x18 +#define GIC_CPU_ALIAS_BINPOINT 0x1c +#define GIC_CPU_ACTIVEPRIO 0xd0 +#define GIC_CPU_IDENT 0xfc #define GIC_DIST_CTRL 0x000 #define GIC_DIST_CTR 0x004 @@ -31,6 +34,8 @@ #define GIC_DIST_TARGET 0x800 #define GIC_DIST_CONFIG 0xc00 #define GIC_DIST_SOFTINT 0xf00 +#define GIC_DIST_SGI_CLEAR 0xf10 +#define GIC_DIST_SGI_SET 0xf20 #define GICH_HCR 0x0 #define GICH_VTR 0x4 @@ -54,6 +59,15 @@ #define GICH_LR_ACTIVE_BIT (1 << 29) #define GICH_LR_EOI (1 << 19) +#define GICH_VMCR_CTRL_SHIFT 0 +#define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT) +#define GICH_VMCR_PRIMASK_SHIFT 27 +#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) +#define GICH_VMCR_BINPOINT_SHIFT 21 +#define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) +#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 +#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) + #define GICH_MISR_EOI (1 << 0) #define GICH_MISR_U (1 << 1)