From patchwork Tue Oct 29 12:20:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 3107871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 460E29F2B7 for ; Tue, 29 Oct 2013 12:22:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D733A20218 for ; Tue, 29 Oct 2013 12:22:21 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C9CC202C8 for ; Tue, 29 Oct 2013 12:22:19 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vb8If-0007yd-93; Tue, 29 Oct 2013 12:21:33 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vb8IW-00032v-A6; Tue, 29 Oct 2013 12:21:24 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vb8I6-0002yB-9w for linux-arm-kernel@lists.infradead.org; Tue, 29 Oct 2013 12:21:02 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 29 Oct 2013 05:20:22 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 29 Oct 2013 05:20:08 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 29 Oct 2013 05:20:08 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.327.1; Tue, 29 Oct 2013 05:20:38 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Tue, 29 Oct 2013 05:20:38 -0700 Received: from ldewangan-ubuntu.nvidia.com (dhcp-10-19-65-30.nvidia.com [10.19.65.30]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r9TCKPI7018250; Tue, 29 Oct 2013 05:20:34 -0700 (PDT) From: Laxman Dewangan To: , , , , Subject: [PATCH 2/4] clk: as3722: add clock driver for ams AS3722 Date: Tue, 29 Oct 2013 17:50:03 +0530 Message-ID: <1383049205-29620-3-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1383049205-29620-1-git-send-email-ldewangan@nvidia.com> References: <1383049205-29620-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131029_082058_683424_D6C8FD34 X-CRM114-Status: GOOD ( 21.55 ) X-Spam-Score: -2.4 (--) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, rob.herring@calxeda.com, Laxman Dewangan , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Device ams AS3722 supports one clock 32KHz output. Add clock driver to control the clock through clock framework. Signed-off-by: Laxman Dewangan --- drivers/clk/Kconfig | 8 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-as3722.c | 166 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 175 insertions(+), 0 deletions(-) create mode 100644 drivers/clk/clk-as3722.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 5c51115..03257bf 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -78,6 +78,14 @@ config CLK_TWL6040 McPDM. McPDM module is using the external bit clock on the McPDM bus as functional clock. +config COMMON_CLK_AS3722 + tristate "ams AS3722 clock32K driver" + depends on MFD_AS3722 + help + ---help--- + Supports the clocking subsystem of the ams AS3722 PMIC from ams. + This device supports one 32KHz clock. + config COMMON_CLK_AXI_CLKGEN tristate "AXI clkgen driver" depends on ARCH_ZYNQ || MICROBLAZE diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index fe3121b..b94624d 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ obj-$(CONFIG_X86) += x86/ # Chip specific +obj-$(CONFIG_COMMON_CLK_AS3722) += clk-as3722.o obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o diff --git a/drivers/clk/clk-as3722.c b/drivers/clk/clk-as3722.c new file mode 100644 index 0000000..9358029 --- /dev/null +++ b/drivers/clk/clk-as3722.c @@ -0,0 +1,166 @@ +/* + * Clock driver for ams AS3722 device. + * + * Copyright (c) 2013, NVIDIA Corporation. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct as3722_clks { + struct device *dev; + struct as3722 *as3722; + struct clk_hw hw; + struct clk *clk; + struct clk_onecell_data clk_data; +}; + +static inline struct as3722_clks *to_as3722_clks(struct clk_hw *hw) +{ + return container_of(hw, struct as3722_clks, hw); +} + +static unsigned long as3722_clks_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 32768; +} + +static int as3722_clks_prepare(struct clk_hw *hw) +{ + struct as3722_clks *as3722_clks = to_as3722_clks(hw); + int ret; + + ret = as3722_update_bits(as3722_clks->as3722, AS3722_RTC_CONTROL_REG, + AS3722_RTC_CLK32K_OUT_EN, AS3722_RTC_CLK32K_OUT_EN); + if (ret < 0) + dev_err(as3722_clks->dev, "RTC_CONTROL_REG update failed, %d\n", + ret); + + return ret; +} + +static void as3722_clks_unprepare(struct clk_hw *hw) +{ + struct as3722_clks *as3722_clks = to_as3722_clks(hw); + int ret; + + ret = as3722_update_bits(as3722_clks->as3722, AS3722_RTC_CONTROL_REG, + AS3722_RTC_CLK32K_OUT_EN, 0); + if (ret < 0) + dev_err(as3722_clks->dev, "RTC_CONTROL_REG update failed, %d\n", + ret); +} + +static int as3722_clks_is_prepared(struct clk_hw *hw) +{ + struct as3722_clks *as3722_clks = to_as3722_clks(hw); + int ret; + u32 val; + + ret = as3722_read(as3722_clks->as3722, AS3722_RTC_CONTROL_REG, &val); + if (ret < 0) { + dev_err(as3722_clks->dev, "RTC_CONTROL_REG read failed, %d\n", + ret); + return ret; + } + + return !!(val & AS3722_RTC_CLK32K_OUT_EN); +} + +static struct clk_ops as3722_clks_ops = { + .prepare = as3722_clks_prepare, + .unprepare = as3722_clks_unprepare, + .is_prepared = as3722_clks_is_prepared, + .recalc_rate = as3722_clks_recalc_rate, +}; + +static struct clk_init_data as3722_clks_hw_init = { + .name = "clk32k", + .ops = &as3722_clks_ops, + .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED, +}; + +static int as3722_clks_probe(struct platform_device *pdev) +{ + struct as3722_clks *as3722_clks; + struct clk *clk; + int ret; + + as3722_clks = devm_kzalloc(&pdev->dev, sizeof(*as3722_clks), + GFP_KERNEL); + if (!as3722_clks) + return -ENOMEM; + + as3722_clks->clk_data.clks = devm_kzalloc(&pdev->dev, + sizeof(*as3722_clks->clk_data.clks), GFP_KERNEL); + if (!as3722_clks->clk_data.clks) + return -ENOMEM; + + platform_set_drvdata(pdev, as3722_clks); + + as3722_clks->as3722 = dev_get_drvdata(pdev->dev.parent); + as3722_clks->dev = &pdev->dev; + as3722_clks->hw.init = &as3722_clks_hw_init; + + clk = devm_clk_register(&pdev->dev, &as3722_clks->hw); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(&pdev->dev, "Fail to register clock %s, %d\n", + as3722_clks_hw_init.name, ret); + return ret; + } + as3722_clks->clk = clk; + as3722_clks->clk_data.clks[0] = clk; + as3722_clks->clk_data.clk_num = 1; + ret = of_clk_add_provider(pdev->dev.parent->of_node, + of_clk_src_simple_get, &as3722_clks->clk_data); + if (ret < 0) + dev_err(&pdev->dev, "Fail to add clock driver, %d\n", ret); + return ret; +} + +static int as3722_clks_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.parent->of_node); + return 0; +} + +static struct platform_driver as3722_clks_driver = { + .driver = { + .name = "as3722-clk", + .owner = THIS_MODULE, + }, + .probe = as3722_clks_probe, + .remove = as3722_clks_remove, +}; + +module_platform_driver(as3722_clks_driver); + +MODULE_DESCRIPTION("Clock driver for ams AS3722 PMIC Device"); +MODULE_ALIAS("platform:as3722-clk"); +MODULE_AUTHOR("Laxman Dewangan "); +MODULE_LICENSE("GPL v2");