From patchwork Tue Oct 29 21:10:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Capper X-Patchwork-Id: 3111731 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3A6A59F2B7 for ; Tue, 29 Oct 2013 21:17:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 614E220203 for ; Tue, 29 Oct 2013 21:17:58 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 636822011B for ; Tue, 29 Oct 2013 21:17:57 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VbGfi-0007Vh-0p; Tue, 29 Oct 2013 21:17:54 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VbGff-0007PT-H4; Tue, 29 Oct 2013 21:17:51 +0000 Received: from mail-we0-f173.google.com ([74.125.82.173]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VbGfd-0007Ob-GS for linux-arm-kernel@lists.infradead.org; Tue, 29 Oct 2013 21:17:50 +0000 Received: by mail-we0-f173.google.com with SMTP id u57so452256wes.18 for ; Tue, 29 Oct 2013 14:17:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Sex8xl0ugci1yDtgu+pImMUuvDyVLO5lUayAU6tOpB0=; b=gEjfgGxwHsLntKYjjJo0pt7zjFgz0zlb/aoUHK9GIF90Rs2bSz85OlPMYVYF7vOFWY 9XKV+1hRDchMAdGsAkDlRX5CgI7PTK+9nCJGZI0VbIaDkvrAS01wCvJbN/oP5B2D0RVh EVC1p8K4nlQDcLWxp2IODyEfcL/6ZJr4NUe7rLlFyTtnIMZgQaQCm76TKDqRe7Cv+1Fq LfvyOk7sJT389Ld2wT/Y+ceVPA4SX+997BaL454kDMbG9408i0NMr/lISMOqTI0FC/Vm wa/bVKRPuQYHUrBgTWc8WPD+brwqTv2fyUS2vXGioIUjw3yyMrgmXk9KR+wGexNwEmxq yrpA== X-Gm-Message-State: ALoCoQm6tFx24ls8+4i6dGRN+sBHBHy3A16/EG7B2Ih/3KlfgNgB4h0B/gVhHB+DutoJS6A1lkRm X-Received: by 10.181.13.173 with SMTP id ez13mr14750624wid.49.1383081080003; Tue, 29 Oct 2013 14:11:20 -0700 (PDT) Received: from marmot.wormnet.eu (marmot.wormnet.eu. [188.246.204.87]) by mx.google.com with ESMTPSA id ey4sm8848624wic.11.2013.10.29.14.11.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Oct 2013 14:11:19 -0700 (PDT) From: Steve Capper To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: Add hwcaps for crypto and CRC32 extensions. Date: Tue, 29 Oct 2013 21:10:38 +0000 Message-Id: <1383081038-3241-1-git-send-email-steve.capper@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131029_171749_637274_D9E0F496 X-CRM114-Status: GOOD ( 13.76 ) X-Spam-Score: -2.6 (--) Cc: Steve Capper , patches@linaro.org, will.deacon@arm.com, ard.biesheuvel@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Advertise the optional cryptographic and CRC32 instructions to user space where present. Several hwcap bits [2-6] are allocated. Signed-off-by: Steve Capper --- arch/arm64/include/uapi/asm/hwcap.h | 6 +++++- arch/arm64/kernel/setup.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index eea4975..2cd54ce 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -21,6 +21,10 @@ */ #define HWCAP_FP (1 << 0) #define HWCAP_ASIMD (1 << 1) - +#define HWCAP_AES (1 << 2) +#define HWCAP_PMULL (1 << 3) +#define HWCAP_SHA1 (1 << 4) +#define HWCAP_SHA2 (1 << 5) +#define HWCAP_CRC32 (1 << 6) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index add6ea6..d7a5f9c 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -100,6 +100,7 @@ void __init early_print(const char *str, ...) static void __init setup_processor(void) { struct cpu_info *cpu_info; + u64 features, block; /* * locate processor in the list of supported processor @@ -120,6 +121,37 @@ static void __init setup_processor(void) sprintf(init_utsname()->machine, "aarch64"); elf_hwcap = 0; + + /* + * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks. + * The blocks we test below represent incremental functionality + * for non-negative values. Negative values are reserved. + */ + features = read_cpuid(ID_AA64ISAR0_EL1); + block = (features >> 4) & 0xf; + if (!(block & 0x8)) { + switch (block) { + default: + case 2: + elf_hwcap |= HWCAP_PMULL; + case 1: + elf_hwcap |= HWCAP_AES; + case 0: + break; + } + } + + block = (features >> 8) & 0xf; + if (block && !(block & 0x8)) + elf_hwcap |= HWCAP_SHA1; + + block = (features >> 12) & 0xf; + if (block && !(block & 0x8)) + elf_hwcap |= HWCAP_SHA2; + + block = (features >> 16) & 0xf; + if (block && !(block & 0x8)) + elf_hwcap |= HWCAP_CRC32; } static void __init setup_machine_fdt(phys_addr_t dt_phys) @@ -309,6 +341,11 @@ subsys_initcall(topology_init); static const char *hwcap_str[] = { "fp", "asimd", + "aes", + "pmull", + "sha1", + "sha2", + "crc32", NULL };